High resolution time measurement in a FPGA

Details High resolution time measurement in a FPGA High resolution time measurement in a FPGA

2011-07-12

2011-07-12

Wachsman, Hal D (Department: 2857)

Data processing: measuring, calibrating, or testing

Calibration or correction system

Timing

C702S078000, C702S079000, C702S125000, C326S037000

Reexamination Certificate

active

07979228

ABSTRACT:
Various techniques are described for high resolution time measurement using a programmable device, such as an FPGA. The timing may be triggered by any event, depending on the applications of use. Once triggering has occurred, a START pulse begins propagating through the FPGA. The pulse is able to propagate through the FPGA in a staggered manner traversing multiple FPGA columns to maximize the amount of time delay that may be achieved while minimizing the overall array size, and thus minimizing the resource utilization, of the FPGA. The FPGA timing delay is calibrated by measuring for the linear and non-linear differences in delay time of each unit circuit forming the staggered delay line path for the timing circuit. The FPGA achieves nanosecond and sub-nanosecond time resolutions and is used in applications such as various time of flight systems.

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