High-resolution synchronous delay line

Details High-resolution synchronous delay line High-resolution synchronous delay line

1993-03-24

1994-11-15

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

328 72, 327237, 327259, 327277, H03K 5159, H03K 700, H03K 301, H03K 1700

Patent

active

053651286

ABSTRACT:
A synchronous delay line (SDL) for generating delayed signals synchronized with a clock signal is described. The present SDL includes a phase generator and a plurality of serially coupled voltage controlled delay elements. The phase generator takes the clock signal and generates a first trigger signal and a second trigger signal, which are substantially deskewed with respect to each other. Each of the delay elements receives two trigger inputs and outputs a delayed signal and two trigger outputs. The first and second trigger signals are coupled to one of the delay elements as trigger inputs. Each transition of the first and second trigger signals triggers the propagation of two waves through the delay line. The present SDL has a minimum tap-to-tap delay of only one inverter delay, versus a minimum tap-to-tap delay of two NAND gates in prior SDLs. Thus, the present SDL provides for double the number of output taps, and hence, double the resolution as compared to prior SDLs.

REFERENCES:
patent: 4496861 (1985-01-01), Bazes
patent: 4975605 (1990-12-01), Bazes
patent: 4994695 (1991-02-01), Bazes
patent: 5036230 (1991-07-01), Bazes
"A CMOS Synchronous Delay Line", Mel Bazes, Intel Technology Journal, Fall 1989.

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