High resolution interleaved delay chain

Details High resolution interleaved delay chain High resolution interleaved delay chain

2003-01-07

2004-08-10

Nuton, My-Trang (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

Reexamination Certificate

active

06774691

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to delay locked loop (DLL) circuits, particularly to delay chains for use in DLL circuits.
BACKGROUND OF THE INVENTION
High speed electronic systems often have critical timing requirements which call for a periodic clock signal having a precise timing relationship with some reference signal. The improved performance of integrated circuits (ICs) and their ever-increasing complexity presents a challenge with respect to keeping such ICs synchronized when inter-operating in ever more complex systems.
The operation of all components in a system should be highly synchronized, i.e., the maximum skew or difference in time between the significant edges of the internal clocking signals of all the components should be minimal. Because different components may have different manufacturing parameters, which when taken together with additional factors such as ambient temperature, voltage, and processing variations could lead to large differences in the phases of the internal clocking signals of the different components, simply feeding a system-wide reference clock to the components may not be sufficient to achieve synchronization.
One way synchronization has been achieved is with the use of delay locked loop (DLL) circuits.
FIG. 1
is a block diagram of a typical DLL circuit. The DLL includes a phase detector
10
which detects the phase difference between an input clock signal and an output clock signal of the same frequency and generates a digital signal related to the phase difference. The phase difference signal is in turn used by a delay control block
20
to control a delay chain
30
which accordingly advances or delays the timing of the output clock signal with respect to the input clock signal until the rising edge of the output clock signal is coincident with the rising edge of the input clock signal. The phase detector
10
, control block
20
and delay chain
30
thus operate in a closed loop to bring the two clock signals into phase and thus synchronize the components whose operations are timed in accordance with the respective clock signals.
Optionally, a feedback delay
40
may be included in the feedback path from the output of the delay chain
30
to the phase detector
10
. The feedback delay
40
can be used to compensate for additional delay to which the output clock may be subjected so that the further delayed output clock will be in phase with the input clock.
The precision with which a DLL circuit can match the phases of two clock signals depends in large part on the resolution of the delay chain used in the DLL. The resolution of the delay chain refers to the size of the delay increments by which an input signal can be delayed. The smaller the delay increments, the finer the resolution of the delay chain. Generally, however, the finer the resolution of the delay chain, the greater its complexity. Furthermore, the delay chain represents the bulk of the complexity of the DLL circuit. It is therefore desirable to achieve fine resolution without unduly increasing the complexity of the delay chain.
FIG. 2
shows a typical delay chain
30
comprising multiple delay elements
120
, each of which introduces the same delay period &tgr;. A clock signal is applied to an input buffer
100
whose output is coupled to the input of a first delay element
120
.
1
whose output is in turn coupled to the input of a further delay element
120
.
2
and so on. The output of the input buffer
100
and of each delay element
120
.
1
-
120
.N is coupled to a respective switch PS
0
-PS
N
. The output of the last delay element
120
.N+1 is not used. The last delay element
120
.N+1 is provided to make the load experienced by the second-to-last delay element
120
.N similar to that experienced by the other delay elements, thus providing a similar response. The outputs of the switches PS
0
-PS
N
are coupled to the input of an output buffer
101
. The delay control logic
20
causes only one of the switches to close at any time thus selecting one of the outputs of the delay elements
120
or input buffer
100
for application to the output buffer
101
.
The output of the output buffer
101
is coupled to the input of a further delay element
121
and to a first input of a phase blender
103
. The output of the delay element
121
is coupled to a second input of the phase blender
103
. The delay &tgr; introduced by the delay element
121
is the same as that of each of the delay elements
120
. The phase blender
103
generates a signal, DLL_clock, which is delayed (in addition to a nominal propagation delay) by a portion of the delay &tgr; between the two inputs of the phase blender. The portion of the delay &tgr; by which the output signal is delayed is selected in accordance with a phase blending control signal which is generated by the delay control logic
20
.
The phase blender
103
can be said to provide a fine adjustment of the delay through the delay chain whereas the multiple delay elements
120
provide a coarse adjustment.
When increasing the delay through the delay chain up to the desired amount, the delay control logic
20
first adjusts the delay through the phase blender
103
. If the maximum delay through the phase blender
103
is not sufficient, however, the control logic controls the switches PS
0
-PS
N
to add an additional increment of delay, &tgr;, and resets the delay through the phase blender. The delay through the phase blender is then adjusted as before and the switches PS
0
-PS
N
may be adjusted, as needed. The process is repeated until the delay chain
30
is configured to introduce the desired amount of delay between the input and output signals.
In order to avoid a sudden jump in the phase of the output signal, the transition in the aforementioned iterative process between the fine and coarse adjustment of the delay through the delay chain, referred to as “fine-to-coarse hand-over,” should be performed so that the addition of the incremental delay &tgr; via the delay elements
120
occurs substantially simultaneously with the resetting of the delay through the phase blender
103
. If a phase jump does occur, however, it will be no larger than &tgr;, the incremental delay amount. At low clock frequencies, any such phase jump introduced by the DLL may not be significant as it represents a small percentage of the clock period. For high frequencies, however, such a phase jump can be intolerable. The presence of such a phase jump, therefore, limits the range of clock frequencies over which a DLL can operate.
One solution is to provide a delay chain having a very high resolution (small &tgr;) so that any phase jump that may occur will be negligible relative to the clock period. This approach, however, adds significantly to the complexity of the delay chain or alternatively reduces the maximum attainable delay of the delay chain and thus the operating range of the DLL.
SUMMARY OF THE INVENTION
The present invention overcomes the above-discussed problems of conventional DLLs by providing a high resolution delay chain that addresses the issue of fine-to-coarse hand-over. The delay chain of the present invention can perform a smooth fine-to-coarse hand-over with no undesirable phase discontinuity.
In an exemplary embodiment of a delay chain of the present invention, a plurality of delay elements are arranged in series. A first delayed clock signal is generated by selecting one of the outputs of a first subset of the plurality of delay elements while a second delayed clock signal is generated by selecting one of the outputs of a second subset of the plurality of delay elements. Numbering the delay elements sequentially in the order in which they are connected, the first subset of delay elements consists of the odd numbered delay elements whereas the second subset of delay elements consists of the even numbered delay elements. The outputs of the delay elements are selected so that when the output of delay element N is selected, the output of delay element N+1 is also selected. The first and second delayed

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