High resolution image processor with multiple bus architecture

Details High resolution image processor with multiple bus architecture High resolution image processor with multiple bus architecture

1994-11-04

1997-01-07

Peng, John K.

Television

Image signal processing circuitry specific to television

With details of static storage device

348718, 348231, 348552, 348426, 345200, 395309, H04N 5907, H04N 700

Patent

active

055922376

ABSTRACT:
A multiple video data bus architecture permits high speed data transfer among the various circuit elements of a fluoroscopic imaging processor. This permits simultaneous acquisition, storage, display, and image enhancement of high resolution, i.e., 2K.times.2K images. A memory interface circuit compresses the video data for storage in bulk memory. The processor supports several high-resolution monitors which can respectively display radiographic images from different subjects, so that review and diagnosis can occur remotely.

REFERENCES:
patent: 4868651 (1989-09-01), Chou et al.
patent: 5179582 (1993-01-01), Keller et al.
patent: 5220312 (1993-06-01), Lumelsky et al.
patent: 5452022 (1995-09-01), Yamamoto et al.
patent: 5481279 (1996-01-01), Honda et al.
patent: 5483296 (1996-01-01), Nonweiler

Affiliated with

Also associated with

Rating

High resolution image processor with multiple bus architecture does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High resolution image processor with multiple bus architecture, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High resolution image processor with multiple bus architecture will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1768736