High resolution frequency synthesis

Telecommunications – Transmitter and receiver at same station – With frequency stabilization

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Details

4551651, 4551821, 4551831, 4551921, 455260, 331 2, 331 25, H04B 140, H04B 1702, H03L 700

Patent

active

051520052

ABSTRACT:
The synthesizer includes an output PLL having a divide-by-N1 divider in its feedback loop. The output PLL is couples through frequency offset circuitry to receive a reference signal from a driver PLL having a divide-by-N2 divider in its feedback loop. Another divide-by-N1 divider coupled a reference oscillator to the driver PLL. The reference oscillator provides another reference signal. As a result, the setting for N1 controls the course frequency tuning and the setting for N2 controls the fine frequency tuning of the synthesizer which provides any one of a plurality of selectable predetermined output frequencies. The adjacent selectable frequencies are closer together than the frequencies of the reference signals. The synthesizer has a simple configuration and provides a high degree of output frequency resolution, fast acquisition and low noise.

REFERENCES:
patent: 4542531 (1985-09-01), Fukumura
patent: 4593411 (1986-06-01), Schiller
patent: 4791387 (1988-12-01), Hasegawa et al.
patent: 4940950 (1990-07-01), Helfrick
patent: 4963838 (1990-10-01), Hapeyama
IEEE, vol. CE-24, No. 1, Feb. 1978 "A New Design Technique for Digital PLL Synthesizers", BREEZE,E.

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