High resolution digital delay circuit for PLL and DLL

Details High resolution digital delay circuit for PLL and DLL High resolution digital delay circuit for PLL and DLL

2006-10-24

2006-10-24

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S272000, C327S273000

Reexamination Certificate

active

07126404

ABSTRACT:
High resolution digital delay circuits and methods are provided. A multiplexer receives the outputs of first and second delay elements. At least the second delay element is adjustable using a digital control signal. The multiplexer and the first delay element form a first delay loop. The multiplexer, the first delay element and the second delay element form a second delay loop. A logic circuit monitors the number of times (M) that a signal cycles through the first loop. After M reaches a predetermined value (i.e., when the signal is delayed by a predetermined delay), the multiplexer receives a control signal that causes the second loop to close. A signal cycles through the second loop, which provides additional delay. Preferably, the signal cycles through the second loop only once. Generally, this causes the resolution of the delay circuit to be proportional to the minimum delay adjustment of the second delay element.

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Sheng Ye et al. “Techniques for Phase Noise Suppression in Recirculating DLLs”, IEEE Journal of Solid State Circuits, vol. 39, No. 8, Aug. 2004, pp. 1222-1230.

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