High resolution digital clock multiplier

Details High resolution digital clock multiplier High resolution digital clock multiplier

2004-08-16

2008-10-28

Ahn, Sam K (Department: 2611)

Pulse or digital communications

Synchronizers

Reexamination Certificate

active

07443937

ABSTRACT:
A high resolution programmable clock synthesizer that is portable across processes and, thus, process independent is disclosed herein. The clock synthesizer provides a dynamic solution, in that the frequency of the desired clock signal is programmable. Initially, a control unit monitors the input clock signal and the output clock signal to provide the appropriate control signals to a delay string buffer and a fine tuning unit based upon the desired frequency of the output clock signal. While the delay string buffer provides a coarse adjustment to the input clock signal, fine control is provided through the use of the fine tuning unit which further adjustments to the input clock signal. This clock synthesizer exceeds the accuracy of known delay line oscillators by using drive strengths of the in-loop elements to provide a better granularity for the clock synthesizer. Thereby, high resolution is achieved through the use of coarse adjustment and fine adjustment.

REFERENCES:
patent: 5552726 (1996-09-01), Wichman et al.
patent: 6441662 (2002-08-01), Ikeda
patent: 6677794 (2004-01-01), Kim
patent: 7057418 (2006-06-01), Fu et al.
patent: 2003/0235260 (2003-12-01), Nakamura et al.

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