High resolution delay line architecture

Details High resolution delay line architecture High resolution delay line architecture

2005-07-27

2009-12-01

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S261000, C327S276000, C327S277000

Reexamination Certificate

active

07626435

ABSTRACT:
A delay line architecture is presented. In one embodiment, the delay line is used to introduce delay compensation into a circuit design at the top level of the circuit design.

REFERENCES:
patent: 5764096 (1998-06-01), Lipp et al.
patent: 6390579 (2002-05-01), Roylance et al.
patent: 6642760 (2003-11-01), Alon et al.
patent: 6774693 (2004-08-01), Carr
patent: 7135906 (2006-11-01), Takai et al.
patent: 7154323 (2006-12-01), Yamawaki
patent: 2005/0242864 (2005-11-01), Kawasaki et al.
patent: 2006/0066372 (2006-03-01), Collins et al.
patent: 2006/0087353 (2006-04-01), Minzoni et al.

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