High resolution charge-redistribution A/D converter

Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion

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341156, H03M 114

Patent

active

052587614

ABSTRACT:
A circuit technique to achieve 14-bit resolution in a charge-redistribution CMOS analog-to-digital converter. The sign bit plus the six most significant bits are obtained using a 6-bit capacitor array, the next five bits are determined using a resistor array, and finally the last two bits are obtained by use of a second 2-bit capacitor array. The area of the resulting 14-bit A/D converter is not appreciably larger than a corresponding 12-bit A/D converter. The 6-bit capacitor array is realized by connecting unit capacitors of a unit capacitor array. In the second capacitor array, at least one of the capacitors is realized by subdividing the unit capacitor. Since the accuracy of capacitors in the second capacitor array need not be as great as the accuracy of capacitors in the 6-bit capacitor array, subdividing the unit capacitor does not affect the accuracy of the converter.

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patent: 4380756 (1983-04-01), Worsman
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patent: 4908620 (1990-03-01), Fujisawa
patent: 5006853 (1991-04-01), Kiriaki et al.
patent: 5138319 (1992-08-01), Tesch

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