Semiconductor device manufacturing: process – Making passive device – Resistor
Reexamination Certificate
1999-08-27
2003-07-01
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making passive device
Resistor
C438S238000
Reexamination Certificate
active
06586310
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to semiconductor devices and, more specifically, to a semiconductor device having a high resistivity silicon carbide film for use with a four transistor static random access memory (4T SRAM).
BACKGROUND OF THE INVENTION
Semiconductor devices, especially those that pertain to computer and telecommunications applications, have continued to be a focus for enhancing performance. Both smaller device size and higher speed of operation are performance targets. One of the main areas of focus is in forming memory devices. Transistors have been continually reduced in size as the ability to construct smaller gate structures has improved. As the size of transistors has decreased, the size of other components have become the limiting factor in increasing overall component densities.
Resistors, especially those requiring larger values of resistance, have tended to present a problem in reducing component size. The resistance of a material, having a constant height, varies directly with the product of its electrical resistivity (also called its sheet resistance) and the ratio of its length divided by its width. Semiconductor device resistors are often formed as a serpentine planar structure having a constant width. Therefore, a resistor formed from a given material and having twice the value of another resistor formed from the same material would typically require twice the surface area or “real estate” in a semiconductor device.
Conventional semiconductor device resistor materials include polysilicon and amorphous silicon. The band gap for polysilicon is in the 1.6 eV to 1.8 eV range. Whereas for amorphous silicon, the band gap is in the 1.3 eV to 1.4 eV range. These values indicate that the resistivity of polysilicon is generally greater than the resistivity of amorphous silicon. These band gaps generally dictate that a given area of semiconductor device real estate would support larger resistor values using polysilicon than could be supported using amorphous silicon.
The thermal stability of the resistor (and therefore a selected resistor material) is another factor that impacts the choice of the material. If the material does not have sufficient thermal stability, the resistor value will vary too greatly with temperature thereby causing possible malfunction of the circuit. Additionally, poor thermal stability of the material may also contribute to a buildup of leakage currents in the semiconductor device that causes device overheating, which may lead to device failure. This is especially critical for large device-count environments such as memories.
Accordingly, what is needed in the art is a way to construct resistor components that require less device area and provide enhanced thermal characteristics.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides a method of manufacturing a resistor for use in a memory element and a semiconductor device employing the resistor. In one embodiment, the method of manufacturing comprises forming a dielectric layer over an active region of a semiconductor wafer and forming a resistive layer on the dielectric layer. The resistive layer comprises a compound wherein a first element of the compound is a Group III or Group IV element and a second element of the compound is a Group IV or Group V element. The method further comprises connecting an electrical interconnect structure to the resistive layer that electrically connects the resistive layer to the active region.
The present invention therefore introduces the pervasive concept of manufacturing a semiconductor device having a unique resistor composition. The resistor composition of the present invention permits a reduced resistor structure size that better accommodates a larger number of smaller device geometries thereby improving overall device densities. The radiation hardness of the resistor composition is also greatly improved over the use of single, poly or amorphous silicon. Additionally, the resistor composition affords more thermal stability and allows a broader temperature operating range than single, poly or amorphous silicon.
In an embodiment to be illustrated and described, forming a resistive layer includes forming a silicon carbide layer. The silicon carbide layer may be formed with physical vapor deposition. Alternately, forming the resistive layer includes employing chemical vapor deposition. Using chemical vapor deposition includes forming the resistive layer with a forming gas containing silicon and carbon, such as silane (SiH
4
) and methane (CH
4
), having a gas flow ranging from about 1 standard cubic centimeter per minute (sccm) to about 20 sccm, a pressure ranging from about 5 torr to about atmospheric, and a temperature ranging from about 700° C. to about 950° C. Of course, the use of any current or future developed deposition process and appropriate deposition material are well within the broad scope of the present invention.
A resistive layer, in an alternate embodiment, may be formed using a gallium nitride layer. Other appropriate compounds may be selected, by one skilled in the appropriate art, to form a resistive layer having a band gap of at least about 2 eV. An amorphous resistive layer may be formed, in yet another embodiment of the present invention. Forming the amorphous resistive layer includes forming the resistive layer at a temperature of about 25° C. Additionally, forming a resistive layer may include using a pressure ranging from about 2 millitorr to about 10 millitorr. Of course other temperatures and pressures are well within the scope of the present invention.
Forming a semiconductor device on a semiconductor wafer substrate, in an alternate embodiment, comprises forming an active region in the semiconductor wafer substrate, which includes a gate on the semiconductor wafer substrate. A dielectric layer is formed over the active region and gate. A resistive layer is formed over the dielectric layer and is comprised of a compound wherein a first element of the compound is a Group III or Group IV element and a second element of the compound is a Group IV or Group V element. An electrical interconnect structure is connected to the resistive layer that electrically connects the resistive layer to the active region.
In another aspect, the present invention provides a semiconductor device formed on a semiconductor wafer, comprising a transistor located on the semiconductor wafer, and a dielectric layer located over the transistor. The resistor includes resistive layer located over the dielectric layer. The resistive layer comprises a compound wherein a first element of the compound is a Group III or Group IV element and a second element of the compound is a Group IV or Group V element. An interconnect structure electrically connects the resistor to the transistor.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
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patent: 0
Choi Seungmoo
Hamad Amal M.
Llevada Felix
Saxena Vivek
Yih Paul
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