High reliability triple redundant latch with voting logic on...

Details High reliability triple redundant latch with voting logic on... High reliability triple redundant latch with voting logic on...

2007-02-20

2007-02-20

Lee, Calvin (Department: 2818)

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

With electrical circuit layout

C365S199000

Reexamination Certificate

active

11074526

ABSTRACT:
In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, three voting structures with inputs from the first, second, and third settable memory elements and control to the settable memory elements determine the logical values held on the settable memory elements. The propagation delay through a latch is the only propagation delay of the triple redundant latch.

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