High reliability triple redundant latch with integrated...

Details High reliability triple redundant latch with integrated... High reliability triple redundant latch with integrated...

2006-08-22

2006-08-22

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S198000, C327S199000, C327S200000

Reexamination Certificate

active

07095262

ABSTRACT:
In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch with integrated testability. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, a voting structure with inputs from the second settable memory element, the third settable memory element and control to the settable memory elements determine the logical value held on the first settable memory element. Data may be scanned into and out of the second settable memory element. Data is propagated through the buffer into the third settable memory element. The third settable memory element may be used to scan data out of the triple redundant latch. The propagation delay through a latch is the only propagation delay of the triple redundant latch.

REFERENCES:
patent: 6504411 (2003-01-01), Cartagena
patent: 6825691 (2004-11-01), Chu et al.
patent: 6882201 (2005-04-01), Koch et al.
patent: 6930527 (2005-08-01), Cabanas-Holmen et al.
patent: 6937527 (2005-08-01), Lotz et al.
patent: 2002/0095641 (2002-07-01), Cartagena
patent: 2005/0162185 (2005-07-01), Satsukawa

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