High reliability, low leakage, self-aligned silicon gate FET and

Details High reliability, low leakage, self-aligned silicon gate FET and High reliability, low leakage, self-aligned silicon gate FET and

1974-11-06

1976-03-09

Gensler, Paul L.

357 41, 357 54, H01L 2978

Patent

active

039435423

ABSTRACT:
An improved FET structure and method of making same is disclosed. The gate structure of the FET includes a phospho-silicate glass as the insulator and polysilicon as the gate conductor. A thin layer of silicon nitride is formed over the polysilicon and selectively etched so as to remain only over gate areas and other areas where it is desired to extend the polysilicon as a conductor. The unmasked polysilicon is oxidized to form the thick oxide surface coating. The disclosure also describes the use of oxide rings and epitaxial layers to reduce parasitic effects between adjacent FET devices in an integrated circuit.

REFERENCES:
patent: 3633078 (1972-01-01), Dill et al.
patent: 3649884 (1972-03-01), Haneta
patent: 3751722 (1973-08-01), Richman
patent: 3865652 (1975-02-01), Agusta et al.
patent: 3883372 (1975-05-01), Lin

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