High reliability, low leakage, self-aligned silicon gate FET and

Details High reliability, low leakage, self-aligned silicon gate FET and High reliability, low leakage, self-aligned silicon gate FET and

1975-11-06

1977-10-25

Tupman, W.

Metal working

Method of mechanical manufacture

Assembling or joining

29578, B01J 1700

Patent

active

040549895

ABSTRACT:
An improved FET structure and method of making same is disclosed. The gate structure of the FET includes a phospho-silicate glass as the insulator and polysilicon as the gate conductor. A thin layer of silicon nitride is formed over the polysilicon and selectively etched so as to remain only over gate areas and other areas where it is desired to extend the polysilicon as a conductor. The unmasked polysilicon is oxidized to form the thick oxide surface coating. The disclosure also describes the use of oxide rings and epitaxial layers to reduce parasitic effects between adjacent FET devices in an integrated circuit.

REFERENCES:
patent: 3751722 (1973-08-01), Richman
patent: 3761327 (1973-09-01), Harlow
IBM Technical Disclosure Bulletin, "Programmable . . . FET", Chiu, vol. 14, No. 11, Apr. 1972, p. 3356.

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