Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2001-05-29
2004-04-20
Cuneo, Kamand (Department: 2827)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C439S065000
Reexamination Certificate
active
06723927
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to electronic packaging structures such as printed circuit boards, circuit modules, or the like and, more particularly, to those structures requiring special plating processes such as gold plating for electrical contact.
BACKGROUND OF THE INVENTION
The current trend in the design of high speed electronic systems is to provide both high density and highly reliable interconnections between various circuit devices, which form important parts of these systems. The system may be a computer, a telecommunications network device, a handheld “personal digital assistant”, medical equipment, or any other electronic equipment. High reliability for such connections is essential due to potential end product failure, should vital misconnections of these devices occur. Further, to assure effective repair, upgrade, and/or replacement of various system components (i.e., connectors, cards, chips, boards, modules, etc.), it is also highly desirable that such connections be separable and reconnectable in the field within the final product. Also, with financial pressures on manufacturers to be cost competitive, is also important that high-dollar-value assemblies be reworkable to maximize yields and minimize the dollar-value of material to be scrapped.
Historically, connectors on computer motherboards used for allowing field-separable interconnection of semiconductor devices, such as microprocessors and memory modules, were primarily pin-grid-array (PGA) or spring loaded edge connector technology. Such connector technologies allow field upgrade or replacement of defective devices.
But as system density, input/output (I/O) array size and performance have increased so dramatically, so have the stringent specifications for interconnections. These demanding requirements, especially when coupled with the requirement for field-separability, have led to a wide variety of possible connector solutions, the majority of them requiring that mating pads on the motherboard be plated with a precious metal to ensure a reliable and repeatable electrical contact. This additional requirement adds cost to the motherboard so that such practice is not widely implemented.
A land grid array (LGA) is an example of such a connection in which the two primarily parallel circuit elements are connected. Each element has a plurality of contact points or pads, arranged in a linear or two-dimensional array. An array of interconnection elements, known as an interposer, is placed between the two arrays and provides the electrical connection between the contact points or pads. While LGA interposers described in the prior art are implemented in many different ways, the implementations of most interest are those described in the referenced copending U.S. patent applications.
Contact pads on motherboards commonly comprise copper and have a barrier layer of nickel followed by a thin (e.g., 0.001 inch) layer of gold. This plating combination works well for ball grid array (BGA) solder interconnections. It does not work as well, however, for LGA connectors, where a thicker layer of gold is required to ensure a reliable interconnection. Since a thicker gold layer is more costly than a thinner layer, motherboard manufacturers are reluctant to implement such a change.
One solution is proposed in the IBM Technical Disclosure Bulletin, Volume 37, Number 02A, pp. 277 and 278, published in February 1994. It describes an interposer that unfortunately falls short in meeting the requirements of present-day systems. This interposer is proposed to provide an array of electrical contact pads on a first surface for connection to an LGA connector, and on a second surface for BGA solder attachment to a motherboard. However, during service the solder interconnections will creep, thereby relaxing the contact force on individual contact members to the point that the LGA connector loses electrical contact.
A solution to this shortcoming is to provide a spacer of sufficient height to ensure that contact force is maintained at a relatively high level to ensure reliable connections but not so high as to prevent good BGA solder interconnections for all contacts. The concern is that some of the solder interconnections will not make electrical contact due to the non-planarity of the mating surfaces.
It is believed that a high reliability interposer that reduces the cost of a motherboard, while solving the solder creep problem discussed above, constitutes a significant advancement in the art.
It is, therefore, an object of the invention to enhance the electrical interconnection art.
It is another object of the invention to provide an interposer for high reliability that reduces the cost of a motherboard.
It is an additional object of the invention to provide an interposer that ensures the reliability of LGA connectors especially at high temperatures.
SUMMARY OF THE INVENTION
In accordance with the present invention, there is provided an interposer that functions as a high reliability interface between an LGA connector and a motherboard. The novel interposer overcomes the limitations of prior art interposers by including a stepped spacer for each solder interconnection which prevents the relaxation of mechanical contact force while ensuring the integrity of each solder interconnection. The interposer provides noble metal plated contact pads on a first surface to receive the contact members of an LGA connector, and contact pads for BGA solder connections for attachment to a motherboard. A description of the processes to manufacture the interposer is also disclosed.
REFERENCES:
patent: 4029375 (1977-06-01), Gabrielian
patent: 4553192 (1985-11-01), Babuka et al.
patent: 5818700 (1998-10-01), Purinton
patent: 5880590 (1999-03-01), Desai et al.
patent: 5893765 (1999-04-01), Farnworth
patent: 5984691 (1999-11-01), Brodsky et al.
patent: 6044548 (2000-04-01), Distefano et al.
patent: 6219253 (2001-04-01), Green
patent: 6332782 (2001-12-01), Bezama et al.
patent: 6428328 (2002-08-01), Haba et al.
patent: 6495462 (2002-12-01), Haba et al.
IBM Technical Disclosure Bulletin vol. 37, No. 02A Feb. 1994, pps. 277-278. “Improved and Cost-Reduced Interposer for Higher-Risk Processes”.
Fan Zhineng
Le Ai D.
Li Che-Yu
Cuneo Kamand
High Connection Density Inc.
Norris Jeremy
Salzman & Levy
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