High reliability active-standby clock arrangement

Details High reliability active-standby clock arrangement High reliability active-standby clock arrangement

1978-03-20

1979-05-22

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307269, 307219, 328104, H03K 300

Patent

active

041562003

ABSTRACT:
A clock pulse circuit is disclosed in which two clock pulse generators operate in an active-standby circuit arrangement to provide a highly reliable single clock output signal comprising a sequence of repetitive pulses. The arrangement comprises a plurality of counters to count pulses generated by each of the clock pulse generators. Comparison circuitry connected to the counters generates an inequality signal indicative of an apparent failure of one of the generators. Logic circuitry responsive to the inequality signal will cause subsequent clock output pulses to be derived from the operating pulse generator. In one embodiment of this invention an actual failure is distinguished from an allowable phase drift of the generator output signal. Another embodiment utilizes additional counters responsive to complementary generator output signals to maintain an uninterrupted sequence of clock output pulses regardless of a failure in either pulse generator.

REFERENCES:
patent: 3289097 (1966-11-01), Martin
patent: 3479603 (1969-11-01), Overstreet, Jr.
patent: 3751685 (1973-08-01), Jaeger

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