High read speed multivalued read only memory device

Details High read speed multivalued read only memory device High read speed multivalued read only memory device

1998-02-26

1999-09-14

Nelms, David

Static information storage and retrieval

Floating gate

Particular biasing

365 94, G11C 1606, G11C 1700

Patent

active

059532521

ABSTRACT:
In a multivalued read only memory device, a plurality of memory cells each for storing N (N=3, 4, . . . ) information states corresponding to N threshold voltages are connected to word lines, and a plurality of reference memory cells for storing said N information states are connected to a reference word line. A word line selecting circuit selects one of the word lines and selects the reference word line, so that the voltages at the selected word line and at the reference word line are gradually increased. A latch timing generating circuit generates latch timing signals in accordance with output signals of the reference memory cells, and a latch circuit latches an output signal of the memory cells in accordance with the latch timing signals. An encoder circuit generates output data in accordance with output signals of the latch circuit.

REFERENCES:
patent: 4648074 (1987-03-01), Pollachek
patent: 5297084 (1994-03-01), Ban
patent: 5526306 (1996-06-01), Hikawa et al.
patent: 5680343 (1997-10-01), Kamaya
patent: 5721701 (1998-02-01), Ikebe et al.

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