High rate running digital sum-restricted code

Details High rate running digital sum-restricted code High rate running digital sum-restricted code

2006-02-21

2006-02-21

Williams, Howard L. (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

To or from minimum d.c. level codes

C341S059000, C360S048000, C369S059250

Reexamination Certificate

active

07002492

ABSTRACT:
A method and apparatus are provided for encoding successive data words into respective code words. Each data word is mapped into data segments that are constrained to a first number of bit patterns, which is less than a second number of bit patterns that satisfy a first constraint. The data segments are encoded into intermediate code word segments selected from a first set of the bit patterns that satisfy the first constraint, wherein at least some of the bit patterns in the first set violate a second constraint. The intermediate code word segments are encoded into respective code word segments by encoding the intermediate code word segments that violate the second constraint with code word segments selected from a second, different set of the bit patterns that satisfy the first constraint and the second constraint.

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