High quality oxide for use in integrated circuits

Details High quality oxide for use in integrated circuits High quality oxide for use in integrated circuits

2000-06-20

2002-12-10

Tran, Minh Loan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

With means to control surface effects

Insulating coating

C257S635000

Reexamination Certificate

active

06492712

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an ultra-thin oxide for use as the gate dielectric in metal oxide semiconductor (MOS) structures.
BACKGROUND OF THE INVENTION
As integrated circuit (IC) complexity increases, the size of devices within the IC must decrease. To decrease the size of a device, the various elements of a device must be reduced proportionately. This is known as device scaling. In one type of device, a metal-oxide-semiconductor (MOS) structure, device scaling requires that the oxide layer be made thinner. Unfortunately, as conventional oxides are made thinner (scaled), their quality tends to degrade. The degradation in oxide quality tends to adversely impact the reliability of a device using the oxide.
In addition to oxide quality, the reliability of the dielectric material in a MOS structure may be affected by oxide stress and the planarity of the oxide-substrate interface. Oxide stress can result from lattice mismatch and growth induced stress. Lattice mismatch is difficult to overcome and growth stress has been addressed in a variety of ways with mixed results. Stress in the oxide may lead to defects especially in the interfacial region. This may result in mass transport paths and leakage current.
The reliability of a device is characterized by a few conventional criteria. For example, in a MOS transistor reliability may be characterized in terms of the change in conventional device parameters over time (known as device parameter drift). Additionally, time-dependent dielectric breakdown (TDDB) may be used to characterize reliability of the transistor.
Under operating bias (applied voltage) and temperature conditions, device parameters such as threshold voltage (V
t
), saturation current (I
DSAT
) and transconductance (g
m
) tend to drift to unacceptable values. In fact, the drift in device parameters during normal operation is thought to be more problematic than other known reliability problems, such as dielectric breakdown of the oxide. Accordingly, in some cases, device parameter drift can cause a device to fail well before dielectric breakdown occurs.
In order to address the reliability issues discussed above, a variety of approaches have been tried. For example, it is known that the best oxides for many IC devices are grown rather than deposited oxides. Furthermore, the higher growth temperatures may yield a better quality oxide. Unfortunately, there are problems associated with fabricating oxides at high temperatures by conventional techniques. For example, in achieving the high temperatures required in the high temperature oxide growth sequence, the overall thickness of the oxide grown tends to increase. As a result the oxide may be too thick for a reduced dimension device. Thus, in the effort to fabricate a better quality oxide, device scaling objectives may be defeated. Moreover, when cooling down from the high growth temperatures, the viscosity of the grown oxide increases and undesired growth induced stress may result. Given these issues, it is customary in the semiconductor industry to grow oxides at a low temperatures. The drawback to this practice is that by growing oxide at lower temperatures, the oxide quality may be compromised. This reduction in quality adversely impacts reliability of the oxide for reasons discussed above.
What is needed, therefore, is a high quality oxide having low stress which is sufficiently thin to meet the demands of device scaling in the semiconductor industry.
SUMMARY OF THE INVENTION
The present invention relates to an oxide for use in integrated circuits. The oxide is disposed over a substrate and the interface between the substrate and the oxide is planar and substantially stress-free. The oxide has a low defect density (D
o
) and a low interface trap density (N
it
). The oxide of the present invention may have a thickness less than 4.0 nm; illustratively, 1.5 nm or less.


REFERENCES:
patent: 5707888 (1998-01-01), Aronowitz
patent: 5739580 (1998-04-01), Aronowitz et al.
patent: 5885870 (1999-03-01), Maiti et al.
patent: 5926741 (1999-07-01), Matsuoka et al.
patent: 6025280 (2000-02-01), Brady et al.
patent: 6210999 (2001-04-01), Gardner et al.
patent: 0 323 071 (1988-12-01), None
patent: 2 056 174 (1981-03-01), None
patent: 01204435 (1989-08-01), None
U.S. patent application Ser. No. 5,622,607, filed Nov. 15, 1991 and issued on Apr. 22, 1997 to Shunpei Yamazaki et al.

Affiliated with

Also associated with

Rating

High quality oxide for use in integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High quality oxide for use in integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High quality oxide for use in integrated circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2998072