High quality isolation structure formation

Details High quality isolation structure formation High quality isolation structure formation

1999-03-08

2001-06-05

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

C438S788000

Reexamination Certificate

active

06242317

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a method of fabricating an isolation structure.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate dielectric thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the FET, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. Additionally, reducing the size, or scale, of the components of a typical transistor also increases the density, and number, of the transistors that can be produced on a given amount of wafer real estate, lowering the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
Typically, overall reduction in scale of the components of a typical transistor to increase the overall speed of the MOSFET or MOS transistor, and to increase the density, and number, of the transistors that can be produced on a given amount of wafer real estate, also requires a reduction in scale of the isolation structures that separate and electrically isolate semiconductor devices from each other. For example, in a CMOS device, an isolation structure is typically used to separate and electrically isolate the NMOS transistor from the PMOS transistor. It has proven difficult to form scaled-down isolation structures that reduce or eliminate charge-trapping in the isolation structures. It has also proven difficult to integrate the formation of isolation structures with the formation of gate dielectrics for MOS transistors, for example. Typically, isolation structures are disadvantageously exposed during subsequent processing, and this reduces the reliability of the isolation structures and of the semiconductor devices in which such isolation structures are contained.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a method is provided for fabricating an isolation structure, the method including forming a first dielectric layer above a structure and forming an opening in the first dielectric layer and the structure, the opening having sidewalls and a bottom. The method also includes forming a second dielectric layer within the opening on a first portion of the sidewalls and above the bottom of the opening. The method further includes forming a third dielectric layer within the opening adjacent the second dielectric layer and on a second portion of the sidewalls of the opening. The method also further includes passivating bonds in the third dielectric layer to reduce charge-trapping in the third dielectric layer, forming dielectric spacers within the opening adjacent the third dielectric layer and forming a dielectric filler within the opening adjacent the dielectric spacers and above the third dielectric layer.


REFERENCES:
patent: 6074919 (2000-06-01), Gardner et al.
patent: 6100205 (2000-08-01), Liu et al.

Affiliated with

Also associated with

Rating

High quality isolation structure formation does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High quality isolation structure formation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High quality isolation structure formation will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2527797