High quality factor capacitor

Electricity: electrical systems and devices – Electrostatic capacitors – Fixed capacitor

Reexamination Certificate

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Details

C361S306300, C257S532000

Reexamination Certificate

active

06208500

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the fabrication of semiconductor devices. Specifically this invention identifies new layout techniques for fabricating high quality capacitors on semiconductor devices.
2. Description of the Prior Art
The quality factor (i.e. electrical engineering symbol “Q”) of a resonant circuit or component is defined as the ratio of the energy stored in a reactive component, such as a capacitor, to the energy dissipated in a resistive component. For simple resistor-inductor-capacitor circuits, the inductor and capacitor store energy while the resistor dissipates some of the energy. Intuitively, if the resistance is large, any initial oscillation will quickly decay to zero. A small resistance will keep the circuit oscillating longer. In the case of the capacitor, Q is defined as:
Q
=
Energy



Stored



(
C
)
Energy



Dissipated



(
R
)
=
Pwr

(
C
)
*
t
Pwr

(
R
)
*
t
(
1
)
As can be seen in equation (1), Q is inversely proportional to the resistance. The main component relating to the quality factor of a capacitor is the series resistance inherent within the device. To achieve a high Q, the resistance in the capacitor, as shown in equation (1), should be minimized.
The current state of the art, as shown in
FIG. 1
, describes a capacitor layout where the top and bottom conductive plates of approximately the same area, are laterally offset to allow for penetration of the contacts on the bottom plate through the layers of the semiconductor. In the prior art, the series resistance is primarily attributable to the significant distance between the top and bottom plate contacts.
Therefore, a need existed to provide a new layout that reduces the distance between contacts which then reduces the intrinsic resistive component of a capacitor as shown in equation (1). Upon achieving a reduction in the series resistance, the quality factor of the capacitor may be optimized.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a new layout technique for a capacitor on a semiconductor device.
It is another object of the present invention to provide a new layout technique which improves the quality factor of the capacitor.
It is another object of the present invention to provide a new layout technique which reduces the series resistance intrinsic to a capacitor.
It is another object of the present invention to provide a new layout technique which provides cost efficient fabrication.
In accordance with one embodiment of the present invention, an improved layout technique for a capacitor is comprised of at least one bottom conductive plate, a dielectric layer coupled to the at least one bottom plate, a plurality of top conductive plates coupled to the dielectric layer, a plurality of metal contacts coupled to the at least one bottom conductive plate wherein at least one of the plurality of contacts is located between a gap created by two of the plurality of the top conductive plates and a second plurality of metal contacts coupled to the plurality of top conductive plates.
In accordance with another embodiment of the present invention, the bottom conductive plate may be a single plate.
In accordance with another embodiment of the present invention, the bottom conductive plate may be a plurality of conductive plates.
In accordance with another embodiment of the present invention an improved layout technique for a high Q capacitor comprises a bottom conductive plate, a dielectric layer coupled to the at least one bottom plate, a top conductive plate couple to the dielectric layer wherein the top conductive plate comprises a plurality of apertures, a plurality of metal contacts coupled to the bottom conductive plate wherein at least one of the plurality of metal contacts penetrates at least one of the plurality of apertures without contacting the top conductive plate, and a second plurality of metal contacts coupled to the top conductive plate.
The foregoing and other objects, features, and advantages of the invention will be apparent from the following, more particular, description of the preferred embodiments of the invention, as illustrated in the accompanying drawings.


REFERENCES:
patent: 5479316 (1995-12-01), Smrtic et al.
patent: 5583359 (1996-12-01), Ng et al.
patent: 5608246 (1997-03-01), Yeager et al.
patent: 5917230 (1999-06-01), Aldrich

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