High-Q, variable capacitance capacitor

Electricity: electrical systems and devices – Electrostatic capacitors – Variable

Reexamination Certificate

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C257S532000

Reexamination Certificate

active

06587326

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a high-Q, variable capacitance capacitor (varactor).
2. Description of the Related Art
As is known, one of the problems in manufacturing a varactor is how to obtain a high value of the quality factor Q.
For a better understanding of the problem underlying the present invention, the structure of a known varactor and the dependence of the quality factor Q on the geometry and on the project parameters will now be described.
In
FIG. 1
, a varactor
1
of a known type, with an MOS structure, is formed in a pocket
2
of N

-type silicon. A field oxide layer
3
has an opening delimiting an active area
4
accommodating two access regions
5
, of N
+
-type, mutually distanced by a portion
6
of the pocket
2
, forming a first plate of the varactor. A thin dielectric layer
10
(typically silicon oxide), forming the dielectric of the varactor, is present above the portion
6
of the pocket
2
; a polysilicon strip
11
extends above the thin dielectric layer
10
and forms a second plate of the varactor.
The polysilicon strip
11
extends for the whole width of the active area
4
(in direction z, like the access regions
5
) and also continues above the field oxide layer
3
, where a metal contact
12
is formed for electrical connection to an upper metal interconnecting line, not shown.
The access regions
5
are electrically contacted through contacts not shown.
In the structure of
FIG. 1
, the access regions
5
form silicon access resistances R
si
and the polysilicon strip
11
forms a polysilicon access resistance R
poly
; the sum of the two resistances forms the series resistance R of the varactor
1
.
For the varactor
1
the quality factor Q is given by:
Q
=
R



e

(
Z
)
I



m

(
Z
)
=
1
ω



R



C
=
1
ω



C
o



x

(
R
s



i
+
R
p



o



l



y
)
=
1
ω



C
o



x

(
αρ
s



i

L
W

WL
+
βρ
poly

W
L

WL
)
=
=
1
ω



C
o



x

(
αρ
s



i

L
2
+
βρ
poly

W
2
)
&AutoLeftMatch;
(
1
)
wherein C
ox
is the capacitance of the thin dielectric layer
10
, &agr; and &bgr; are experimental coefficients, dependent upon the technology, L and W are respectively the length and the width of the polysilicon strip
11
and &rgr;
si
and &rgr;
poly
are the sheet resistances of the pocket
2
and of the polysilicon strip
11
.
In (1), the importance of the value of the series resistance R may be clearly seen: the lower this resistance, the higher the value of Q that may be obtained at a given frequency.
In the structure of
FIG. 1
, the silicon access resistance R
si
may be minimized using a strongly doped layer (N
+
, for example), autoaligned to the edge of the polysilicon strip
11
and using sufficiently small lengths L.
On the other hand, using small lengths L means having a high polysilicon access resistance R
poly
; normally this resistance is minimized in advanced-type processes by using metal suicides on the gate. This approach, however, imposes restraints as far as regards the maximum length (W) of the structures.
BRIEF SUMMARY OF THE INVENTION
Embodiments of the present invention provide a high-Q, variable capacitance capacitor.
According to one embodiment, the structure is no longer similar to an MOS transistor, but the polysilicon region formed on a thin oxide layer is sided by a portion formed on a thick oxide layer; on the latter portion a contact is formed to allow displacement current to follow a minimum path within a metal line having a low resistivity (for example, of aluminum or tungsten). In this way it is possible to form a structure with a reduced length L and at the same time minimize the polysilicon access resistance R
poly
.


REFERENCES:
patent: 4929989 (1990-05-01), Hayano
patent: 5656834 (1997-08-01), Grzyb et al.
patent: 6396677 (2002-05-01), Chua et al.
patent: 6441449 (2002-08-01), Xu et al.

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