Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2001-02-10
2003-03-18
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S534000, C257S539000, C257S500000, C257S338000, C257S351000
Reexamination Certificate
active
06534843
ABSTRACT:
TECHNICAL FIELD
This invention relates to the design and construction of high-Q inductors within high frequency integrated circuits.
BACKGROUND
The present environment sees the rapid proliferation of wireless communications and the wireless products such as modems, pagers, 2-way radios, oscillators and cell phones which include integrated circuits (ICs) having inductors which operate at high frequencies. There is pressure to make these products more and more efficient, compact, light weight and reliable at radio frequency and microwave frequency. It is efficient and economically desirable to fabricate the maximum number of required devices and elements, including inductors, in a single IC and to limit the number and type of processing steps to ones which are consistent with those presently practiced in IC manufacturing. Pushing the performance of conventional integrated circuits into the high frequency range reveals limitations that must be overcome in order to achieve the desired goal. The inductor is one area which has been examined for optimization.
Quality Factor Q is the commonly accepted indicator of inductor performance in an IC. Q is a measure of the relationship between power loss and energy storage in an inductor expressed as an equation shown as
FIG. 1. A
high value for Q is consistent with sow inductor and substrate loss, low series resistance and high inductance. High frequency is considered be greater than about 500 MHz. To achieve a Q of greater than about 10 would be desirable for that frequency range. The technology of manufacturing ICs over silicon substrates is well established. Unfortunately, a planar spiral inductor fabricated in an IC having a silicon substrate typically experiences high losses at RF, and consequently low Q value. Losses experienced are a result of several factors. Electromagnetic fields generated by the inductor adversely affect the semiconducting silicon substrate as well as devices and conductive lines of which the IC is comprised. The result of this interaction is loss due to coupling, cross talk noise, resistance, parasitic capacitance, reduced inductance and lowering of Q values. Elements of Q with respect to a specific spiral conductor over a silicon substrate are set forth in U.S. Pat. No. 5,760,456, col. 1, line 55 - ff.
One approach to improving the Q factor is to alter the materials of which the IC is comprised. Using substrates other than silicon, such as GaAs and sapphire is possible. However, it would be desirable to maintain manufacturing processes which are as compatible as possible with existing silicon technology, which is well established, rather than to introduce the process changes and to deal with the attendant problems associated with the use of non-silicon substrate materials. U.S. Pat. No. 6,046,109 to Liao et al. describes one approach to improving Q of an IC on a silicon substrate—the creation of isolating regions to separate the inductor from other regions or devices that would otherwise be adversely affected. The isolating regions are created by radiation of, for example, selected silicon semiconductor regions with a high energy beam such as x-rays or gamma rays or by particles such as protons and deuterons, which results in an increase in resistivity of the irradiated area. The depth of penetration of the radiation can be as deep as required to reduce noise, line loss and assure device separation.
Another approach to improving the Q factor is to alter the shape and dimensionality of the inductor itself in order to overcome inherent limitations of the flat spiral inductor. U.S. Pat. No. 6,008,102 to Alford et al. describes two such shapes, toroidal and helical, which are formed in such a way as to align magnetic fields generated by RF currents within the shaped inductor, thereby minimizing dielectric losses, cross talk and increasing Q.
U.S. Pat. Nos. 6,114,937, 5,884,990, 5,793,272 and 6,054,329 to Burghartz et al. describe high Q toroidal and spiral inductors with silicon substrate for use at high frequencies. There are described several embodiments which focus on raising Q by increasing inductance. Devices described that are incorporated in the IC in order to raise Q include: a substrate coated with a dielectric layer having a spiral trench which is capped and lined with a ferromagnetic material in which lies the spiral inductor, connected by via to underpass contact; and/or a second spiral inductor either above or adjacent to the first, the two coils being connected to each other by a ferromagnetic bridge and externally, if stacked, by an overpass. The toroidal inductor is similarly formed in dielectric trenches lined with ferromagnetic material, the coils being segmented to reduce eddy currents and the segments being separated from each other by dielectric, increasing the Q. Studs connect the opposite ends. The ferromagnetic bridge and dummy central structures or air core are stated to increase the Q by reducing flux penetration into the substrate thereby increasing inductance. Use of copper, a low resistance material, in thick interconnects reduces parasitic resistance, further increasing Q. (Aluminum has generally been used.) The patent describes results of Q=40 @ 5.8 GHz for a 1.4 nH inductor and Q=13 @ 600 MHz for a 80 nH inductor, twice or triple the Q than conventional silicon-based integrated inductors.
U.S. Pat. No. 6,037,649 to Liou describes a a three-dimensional coil inductor structure, optionally including a shielding ring, which comprises N-turn coil lines in three levels, separated from each other and the substrate by isolating layers and connected through vias. It is described that the structure of the invention, in which the magnetic field is normal to the substrate, provides lower series resistance than a flat structure, less effect on the other components of the IC, lower parasitic capacitance and higher Q at RF and microwave frequencies.
U.S. Pat. No. 5,559,360 to Chiu et al. describes a multilevel multielement structure that maintains a constant distance between parallel conductive elements, thereby equalizing each element's resistance. The solution is intended to minimize current crowding, especially at conductor widths beyond 15 microns, and maximize self-inductance between conductive elements, possibly raising the Q to 15 for Al conductor over Si substrate.
U.S. Pat. No. 5,446,311 to Ewen et al. describes a multilevel inductor constructed on a silicon substrate which is layered with insulating oxide. The inductors are connected in parallel to avoid series resistance and the metal levels are shunted by vias. A Q of 7 at 2.4 GHz is reported.
U.S. Pat. No. 6,124,624 to Van Roosmalen et al. describes a multilevel inductor comprised of closely spaced stacks of parallel connected elongated rectangular strips in which bridging crossover and/or cross/under is avoided. The levels are separated by silicon dioxide. The structure is stated to raise the Q, possibly over 25 @ 2 GHz, by a reduction of series resistance using various series and parallel connections through vias and by enhanced mutual inductance of layered strips. A staggered stacking is stated to contribute to high Q by reducing parasitic capacitance.
U.S. Pat. No. 6,146,958 to Zhao et al. describes a reduction in series resistance, hence an increase in Q, by connecting a spiral inductor at a lower level to one at a higher level by a continuous via.
Another approach to improving the Q factor is to create shielding or zones within the IC which include materials, or open space, that control or limit the extent that electromagnetic lines can penetrate the IC, thereby reducing substrate losses. U.S. Pat. No. 6,169,008B1 to Wen et al. describes forming a 3-5 micron deep trench in the dielectric substrate of an IC, and filling the trench with a high resistivity epitaxy layer which has a lower dopant concentration than the substrate by several orders of magnitude and will therefor act as a dielectric. The epitaxy layer is etched back, a dielectric layer is deposited over all and the inductor wind
Acosta Raul E.
Carasso Melanie L.
Cordes Steven A.
Groves Robert A.
Lund Jennifer L.
Flynn Nathan J.
Forde Remmon R.
International Business Machines - Corporation
Olsen Judith D.
Trepp Robert M.
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