High pressure reoxidation anneal of silicon nitride for reduced

Details High pressure reoxidation anneal of silicon nitride for reduced High pressure reoxidation anneal of silicon nitride for reduced

1995-10-13

1997-04-29

Tsai, Jey

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

438762, 438770, 438398, H01L 2170, H01L 2700

Patent

active

056248652

ABSTRACT:
A semiconductor integrated circuit fabrication method is provided for forming a capacitor on a semiconductor integrated circuit substrate. A lower capacitor electrode is formed over the semiconductor integrated circuit substrate and a capacitor dielectric is formed over the lower capacitor electrode. The capacitor dielectric is preferably formed of silicon nitride. A reoxidation anneal of the capacitor dielectric is performed at a pressure greater than one atmosphere in order to form an oxide layer over the capacitor dielectric. An upper capacitor electrode is disposed over the oxide layer to form a capacitor. The capacitor is formed as part of a dynamic random access memory cell. A transistor is formed upon the semiconductor integrated circuit substrate and the lower capacitor electrode is formed in electrical contact with a diffusion region of the transistor. The capacitor is formed within an opening in molding material that is deposited over the surface of the semiconductor integrated circuit substrate. The reoxidization anneal of the capacitor dielectric is performed at a temperature in the range of 600.degree. C. to 800.degree. C. at pressures ranging up to twenty-five atmospheres. This forms an oxide layer having a thickness between five angstroms and fifteen angstroms in a period of time short enough to prevent excessive out diffusion of dopants from the diffusion regions of the transistor.

REFERENCES:
patent: 5023683 (1991-06-01), Yamada
patent: 5386382 (1995-01-01), Ahn
patent: 5504029 (1996-04-01), Murata et al.

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