Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Reexamination Certificate
2001-12-14
2004-01-27
Williams, Howard L. (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
C341S156000
Reexamination Certificate
active
06683550
ABSTRACT:
CROSS-REFERENCES TO RELATED APPLICATIONS
Not Applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable.
Reference to Microfiche Appendix
Not Applicable
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
This invention relates generally to circuits for converting electrical signals from analog to digital form, and, more particularly, to applying these circuits in capture instruments for use in automatic test equipment.
DESCRIPTION OF RELATED ART INCLUDING INFORMATION DISCLOSED UNDER 37 C.F.R. 1.97 AND 1.98
Capturing analog signals is a basic function of automatic test equipment for electronics (ATE). A capture instrument converts an analog input signal into a corresponding digital signal, using a circuit conventionally known as an Analog-to-Digital converter, or ADC. As faster and more accurate electronic devices come to market, test systems must be equipped with faster and more accurate ADC's if test systems are to keep pace with advances in new devices. A difficulty arises in the design of ATE, however, because converters that are extremely fast tend to be relatively inaccurate, and converters that are extremely accurate tend to be relatively slow. To promote flexibility for testing a wide range of device characteristics, ATE developers seek to provide both high speed and high accuracy in a single converter topology.
ATE developers have long recognized that the tradeoff between converter speed and accuracy can be somewhat relieved through the use of parallel-connected ADC's. The individual converters from which the parallel topologies have been constructed have customarily been successive approximation converters or flash converters. Parallel connections are established by driving the analog inputs of the ADC's with the same input signal, activating the ADC's simultaneously, and adding the ADCs' outputs to produce a combined digital output signal. Assuming that the noise of each converter exceeds one LSB (Least Significant Bit), the precision of N identical, parallel-connected converters can be increased over the precision of a single converter by approximately log
2
N.
The number of converters cannot be increased indefinitely, however. With each added ADC, cost, space, and especially noise of the overall topology increase. Owing to these diminishing returns, parallel topologies seldom include greater than eight converters. Precision is therefore at most tripled, an improvement that corresponds to fewer than two bits. This level of improvement is generally not enough to allow high-speed ADC's to operate at the level of precision that many applications require. Consequently, the desired combination of speed and precision is generally not attainable at reasonable cost.
BRIEF SUMMARY OF THE INVENTION
With the foregoing background in mind, it is an object of the invention for an ADC topology to be both fast and precise.
To achieve the foregoing object, as well as other objectives and advantages, a parallel topology for converting an analog input signal into a corresponding digital output signal includes a plurality of substantially identical multi-bit sigma-delta stages. Each stage includes a multi-bit sigma-delta loop having an analog input coupled to an input port for receiving the analog input signal and a digital output coupled to a combining circuit. The combining circuit adds the digital outputs of the stages to generate the digital output signal. Noise shaping from the sigma-delta loops increases the precision of the topology beyond that normally achieved using parallel connected converters without sigma-delta loops. This increase in precision allows the topology to be implemented using lower-resolution, higher speed devices than would otherwise be needed.
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Cascaded parallel oversampling sigma-delta modulators Xuesheng Wang; Wei Qin; Xieting Ling Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on , vol. 47 Issue: 2, Feb. 2000, Page(s): 156-161.
Oversampling parallel delta-sigma modulator A/D conversion Galton I.; Jensen, H.T. Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on , vol.: 43 Issue: 12 , Dec. 1996 , Page(s): 801-810.
Effects of quantization noise in parallel arrays of analog-to-digital converters Petraglia, A.; Pinheiro, M.A.A. Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on , vol.: 5 , 1994 , Page(s): 337-340 vol. 5.
Rubenstein Bruce D.
Teradyne, Inc.
Williams Howard L.
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