Pulse or digital communications – Synchronizers
Reexamination Certificate
2006-02-21
2006-02-21
Burd, Kevin (Department: 2631)
Pulse or digital communications
Synchronizers
C375S343000, C375S354000, C327S141000, C370S304000
Reexamination Certificate
active
07003060
ABSTRACT:
An output circuit of the present invention includes a data output circuit and a clock output circuit. The output circuit includes a first D-type flip-flop and a selector for selectively outputting an output from the first D-type flip-flop or second data according to a selection signal. The clock output circuit includes a second D-type flip-flop, a third D-type flip-flop, and a dummy selector circuit. The dummy selector circuit is connected to the second and third D-type flip-flops and outputs a clock signal by using the same elements as those of the selector in order to realize the same delay time as that of the selector.
REFERENCES:
patent: 4904948 (1990-02-01), Asami
patent: 5602878 (1997-02-01), Cross
patent: 5883529 (1999-03-01), Kumata et al.
patent: 6377092 (2002-04-01), Ikeda
patent: 63-254823 (1988-10-01), None
Naka Naoaki
Nakamoto Junko
Arent & Fox PLLC
Burd Kevin
Fujitsu Limited
Torres Juan Alberto
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