Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1999-11-24
2002-09-17
Malzahn, David H. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C345S520000
Reexamination Certificate
active
06453330
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to the field of computer graphics, and more particularly, to high-precision bilinear interpolation.
BACKGROUND OF THE INVENTION
Many applications of modern computer graphics strive to create three-dimensional images on a display device (e.g., a computer monitor) in order to provide a realistic virtual environment. In a typical imaging technique, a three-dimensional object is created by connecting a number of two-dimensional polygons, such as, for example, triangles. Each polygon defines a surface which can be assigned or given a texture, such as wood, stone, fur, hair, scales, and the like, to enhance the realism of the generated object.
Because an object may appear at different perceived distances (e.g., very near, near, far, or very far) during an imaging sequence, a single version of a texture generally cannot be used for all situations. For example, a version of a wood texture which is appropriate for a close-up view of a tree would not be appropriate for a far-away view of the same tree.
Accordingly, for any given texture, a number of multim in parvum (MIP) maps may be provided. Each texture MIP map corresponds to a particular value for level of detail (LOD), which defines how far away a particular object is perceived to be from the viewer of a display. For example, one MIP map may be provided for an object when it should be perceived as being relatively close to a viewer, whereas another MIP map may provided for the same object when it should be perceived as being relatively far from the viewer.
When an object onto which a texture is to be applied does not have the same LOD value as any given MIP map, interpolation can be performed between two MIP maps in order to afford a suitable texture map for that LOD value. When interpolating, it is desirable to provide a high degree of precision so that the displayed image is made to appear as realistic as possible.
SUMMARY OF THE INVENTION
The present invention provides a high-precision bilinear interpolation circuit which provides additional detail for an array of texture elements or “texels” forming at least a portion of a texture map. Each texel has a color or gray scale value. A number of weighting values--each comprising a “weight high” component and a “weight low” component—each define the amount of weight to be given to the color or gray scale value for adjacent texels in an interpolation operation. The present invention provides a circuit which may operate on both components of the weighting values during interpolation utilizing many of the elements typically available in a previously developed circuit for performing trilinear interpolation. The present invention thereby provides greater detail, without a significant increase in area.
According to an embodiment of the present invention, a circuit is provided for performing a high-precision bilinear interpolation operation. The circuit includes a first interpolation operator for interpolating two operands representing a pair of texels using a weight high component of a weighting value. The first interpolation operator outputs a first result. A second interpolation operator interpolates the two operands representing the pair of texels using a weight low component of the weighting value. The second interpolation operator outputs a second result. A combination operator, coupled to the first and second interpolation operators, combines the first and second results.
A technical advantage of the present invention includes forming a high-precision bilinear interpolation circuit using standard hardware elements readily available for implementing a typical trilinear interpolation circuit. Such hardware elements include a plurality of interpolation operators, which are organized as pairs. In accordance with the present invention, for each pair, one interpolation operator operates on the weight high component of a weighting value and the other interpolation operator operates on the weight low component of the weighting value, as explained herein. To the standard hardware elements are added a number of combination operators, each of which is operable to combine the results output by a respective pair of interpolation operators. This affords more detail in a bilinear interpolation operation without significantly increasing the area required for implementation in an integrated circuit (IC) device. In particular, compared to a straightforward method of adding a substantial number of interpolation operators in order to provide more detail, the present invention can provide as much detail without the corresponding cost in surface area in a semiconductor chip implementation. Other aspects and advantages of the present invention are readily apparent to one skilled in the art from the following figures, descriptions, and claims.
REFERENCES:
patent: 5801678 (1998-09-01), Huang et al.
patent: 6219464 (2001-04-01), Greggain et al.
patent: 6348921 (2002-02-01), Zhao et al.
patent: 6373495 (2002-04-01), Lin et al.
Battle James T.
Ng William N.
ATI International SRL
Malzahn David H.
Vedder Price Kaufman & Kammholz
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