High-precision biasing circuit for a cascoded CMOS stage,...

Details High-precision biasing circuit for a cascoded CMOS stage,... High-precision biasing circuit for a cascoded CMOS stage,...

2000-08-28

2002-05-21

Mottola, Steven J. (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including particular biasing arrangement

C330S283000, C330S311000

Reexamination Certificate

active

06392490

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to biasing circuits, and, more particularly, to a high-precision biasing circuit for a CMOS cascode stage with inductive load and degeneration.
The cascode stage includes at least two MOS transistors serially connected between a first voltage reference and a second voltage reference. The present invention has been developed for a low noise amplifier (LNA) having a very large linearity, high gain and ultra low noise (~Pin=−4 dBm, Gain=14 dB, 50 W input/output matching and a noise figure <1.5 dB).
BACKGROUND OF THE INVENTION
On-chip integration of inductors, in CMOS technology is making feasible complete transceivers into a single chip. Moreover, cascode stages with inductive load and degeneration have been recently integrated in low noise amplifiers (LNA) and mixers.
FIG. 1
a
is a schematic example of a single ended LNA, and
FIG. 1
b
is a schematic example of a differential LNA. The amplifier in
FIG. 1
includes a CMOS cascode final stage comprising a first input MOS transistor M
1
and a second common gate MOS transistor M
2
. There is a competitive advantage in using CMOS technology with inductive and noiseless degeneration since the linearity is improved while the inductive load allows the output node to swing over the supply voltage, ensuring a large dynamic range.
FIG. 2
a
is a schematic example of an application where two transistors are in a cascode configuration to achieve a single ended mixer.
FIG. 2
b
is an example of a double cascode transistor configuration to achieve a differential mixer.
Wide dynamic range, large linearity and good noise performance can be achieved at the expense of high current levels. Additionally, the channel length L of the MOS transistor must be kept minimum and the width W must be kept at small to medium values.
The resulting high current density forced through minimum length transistors make them extremely sensitive to what is known as the Early effect. As the load and the degeneration are inductive, the voltage drop Vds(MI) between the drain and source terminals of the first MOS transistor M
1
plus the voltage drop Vds(M
2
) between the drain and source terminals of the second MOS transistor M
2
is equal to the supply voltage Vdd.
To ensure a proper control on gain, noise figure and input impedance, the cascode stage must be biased to take into account the Early effect. Therefore, the CMOS stage must include a noiseless, high precision biasing circuit. This is particularly critical because of the following reasons. The first input transistor M
1
and the second transistor M
2
receive all the DC supply voltage via the gate of the second transistor. Both transistors M
1
and M
2
are also heavily affected by the Early effect. The circuit performances, i.e., voltage gain, input impedance and noise figure, depend heavily upon the biasing current.
The problem of biasing such LNA circuits can be generalized to the problem of biasing a CMOS cascode stage comprising two transistors connected in series and receiving the full DC supply voltage. The gate of the second transistor M
2
is connected to the supply voltage reference Vdd or to a DC potential according to a particular application.
A variety of biasing circuits have been proposed by the known art for solid state amplifiers. Many of these known biasing circuits may be adopted to bias the selective LNA. A commonly used biasing circuit is shown in
FIG. 3
a
and is a circuit derived by a classic cascode current mirror. The resistance Rps represents a DC resistance associated to a non-ideal inductor Ls.
This approach has a drawback due to the fact that the threshold voltage of the transistors M
1
and M
2
is tracked, while the Early effect of the same transistors M
1
and M
2
plus the body effect just of transistor M
2
is not tracked. Others prior art approaches fail for the same reason. The interposition of a current generator connected in series with the transistors M
1
b
and M
2
b
may compensate the Early effect of one of the transistors M
1
or M
2
, but not both, since Vds(M
1
b
)+Vds(M
2
b
)<Vds(M
1
)+Vds(M
2
)=Vdd.
SUMMARY OF THE INVENTION
In view of the foregoing background, it is therefore an object of the present invention to provide a high-precision biasing circuit for a cascode CMOS stage, particularly for low noise amplifiers.
Another object of the present invention is to provide a biasing circuit that does not have internal sensing points.
Yet another object of the present invention is to provide a biasing circuit for a cascode CMOS final output stage driving an inductive load with a proper control gain and noise figure.
Another object of the present invention is to provide the desired biasing conditions for a low noise audio amplifier for wireless communications.
These and other objects, features and advantages in accordance with the present invention are provided based upon a “split biasing technique,” i.e., the task of biasing the cascode stage is split into sub-tasks.
The bias circuit comprises two replicas of the transistors M
1
and M
2
included in the cascode stage, and the desired biasing conditions are forced to one of the replica transistors. Electrical information relevant for the biasing conditions are read from the replica transistor and the desired bias conditions are forced to the other replica transistor using the electrical information previously read.
Another aspect of the present invention relates to a method for biasing a CMOS cascode stage for a low noise amplifier.


REFERENCES:
patent: 4260956 (1981-04-01), Harford
patent: 4528520 (1985-07-01), Osawa
patent: 5563553 (1996-10-01), Jackson
patent: 5717360 (1998-02-01), Vu et al.
patent: 5748040 (1998-05-01), Leung
patent: 5838191 (1998-11-01), Opris et al.
patent: 6271695 (2001-08-01), Gramegna et al.

Affiliated with

Also associated with

Rating

High-precision biasing circuit for a cascoded CMOS stage,... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High-precision biasing circuit for a cascoded CMOS stage,..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High-precision biasing circuit for a cascoded CMOS stage,... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2904108