Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2000-02-22
2001-10-16
Zweizig, Jeffrey (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S382000
Reexamination Certificate
active
06304131
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to voltage regulators, and more particularly to a low drop-out voltage regulator having internal compensation to optimize power supply rejection ripple.
2. Description of the Prior Art
Active compensating capacitive multiplier structures and techniques, e.g. nested Miller compensation, are well known in the art. The specific type of compensating circuit used is dependent upon the particular application. One application of improving phase margin for example, takes advantage of the Miller Effect by adding a Miller compensation capacitance in parallel with a gain stage, e.g., the output stage of a two stage amplifier circuit. Such a configuration results in the well-known and desirable phenomenon called pole splitting, which advantageously multiplies the effective capacitance of the physical capacitor employed in the circuit. See, e.g., for background on compensation of amplifier circuits using Miller-compensating capacitance, Paul R. Gray and Robert g. Meyer,
Analysis and Design of Analog Integrated Circuits,
Third Ed., John Wiley & sons, Inc. New York, 1993, Ch. 9, especially pp. 607-623.
Recent trends associated with high efficiency battery powered equipment are creating increased demand for power management systems using DC/DC converters feeding low drop-out (LDO) voltage regulators. Applications requiring power from such LDO voltage regulators are becoming more sensitive to noise as application bandwidth requirements are pushed ever upward. This places far greater importance on the power supply ripple rejection (PSRR) characteristics associated with LDO voltage regulators since LDO voltage regulators are used to both clean up the output noise of the DC/DC converter and to provide power supply cross talk immunity from application blocks sharing the same raw DC supply.
There is also a trend showing an increased use of ceramic capacitors as output decoupling capacitors as contrasted with the once more typical use of tantalum capacitors in such applications. The significantly low equivalent series resistance (ESR) associated with ceramic capacitors however, makes reliance on ceramic output capacitor ESR characteristics no longer feasible to stabilize an LDO amplifier control loop. Thus, a need exists in the LDO amplifier art for an internal compensation technique allowing use of a wide range of output capacitor types. Such internal compensation techniques would allow the use of much smaller output capacitors and therefore provide a means for reducing both PCB real estate requirements and external component costs.
One widely popular accepted technique associated with internal compensation is known as “Pole splitting” or “Miller Compensation” such as discussed herein above. Miller compensation, however, provides an impedance shunt across the series pass device associated with LDO voltage regulators, via the compensation capacitor and Cgs. This impedance is undesirable since it causes an early roll-off in PSRR.
The conventional two-stage PMOS low drop-out voltage regulator suffers from very poor load regulation at light, or no load, conditions. This is due to the gate of the PMOS series pass being driven from a source follower, Vdsat+Vgs, where Vt can vary from +0.2 to −0.2 V for a natural NMOS device and +0.5 to +0.9 V for a standard device. Such variations will ultimately force the first stage amplifier output devices to enter their triode region (linear mode) when the regulator is lightly loaded, resulting in a significant reduction in loop gain and hence deterioration in regulator performance.
In view of the foregoing, a need exists for an amplifier circuit architecture and technique capable of achieving higher PSRR performance from an internally compensated PMOS low drop-out voltage regulator than that presently achievable using conventional “Miller” or “Pole-splitting” techniques generally known in the art.
SUMMARY OF THE INVENTION
The present invention is directed to a circuit architecture and technique for achieving high power supply ripple rejection (PSRR) from an internally compensated PMOS low drop-out voltage regulator. This high power supply ripple rejection is achieved via a technique that provides a means for extending the PSRR outside of the usual constraints and thus enables high bandwidth PSRR characteristics from a low quiescent-current regulator. The present circuit further provides precise control of a PMOS output series pass device during light
o-load conditions without significant loss of loop gain and thereby provides highly improved no-load regulation.
A conventional PMOS low drop-out voltage regulator is generally comprised of two gain stages in order to promote simplification of any related compensated closed loop system. The input stage of such a voltage regulator is formulated via a differential amplifier. The output stage comprises a series pass PMOS device. These two stages are generally coupled together via an impedance buffer, typically a source follower, to enable the input stage high impedance output to drive the large gate capacitance of the series pass PMOS device and thereby minimize the effect of an internal pole that would otherwise interfere with loop compensation. Miller capacitor multiplication, or “Pole-splitting”, is generally used by those skilled in the art to internally compensate the voltage regulator for use with ceramic output capacitors where the circuit designer cannot rely on an external compensating zero formed by the ESR associated with an electrolytic capacitor. The impedance shunt formed through the Miller compensation capacitor and PMOS Cgs using this approach however, generates a PSRR that rolls off earlier than that associated with the open loop control performance of the regulator. Further, Miller compensation yields disadvantageous no-load regulation since the input stage amplifier output is forced into its linear mode as it tries to keep the output PMOS device in deep sub-threshold/cut-off at very light or no-load conditions. This condition dramatically reduces the voltage gain of the control loop causing degradation in regulator performance.
In view of the foregoing, the present invention provides a structure and technique capable of extending the control bandwidth along with the consequential increase in quiescent current generally associated with Miller compensation and other like compensation approaches, to achieve high PSSR performance from an internally compensated PMOS low drop-out voltage regulator.
A preferred embodiment of the present invention comprises a third amplifier stage configured as a common source, current mirror loaded PMOS device, connected between the input stage differential amplifier and the output PMOS device. This third amplifier stage then replaces the more conventional source follower impedance buffer associated with the above described Miller compensation techniques. Compensation is achieved through use of a small internal capacitor that provides a very low frequency dominant pole at the output of the input amplifier stage while effectively pushing out the two other poles at the outputs of the second and third gain stages to a frequency well outside of the unity gain frequency to ensure closed loop stability.
A feature of the present invention is associated with high, wide bandwidth PSRR achieved through an integrated circuit implementation of three voltage gain stages compensated by a nested active Miller compensation technique that does not impedance shunt the PMOS series pass device.
Another feature of the present invention is associated with a PMOS common source amplifier gate drive circuit that substantially eliminates poor DC load regulation generally identified with conventional source follower drivers.
Yet another feature of the present invention is associated with a flexible internally compensated PMOS low drop-out voltage regulator capable of functioning with a wide range of output capacitors.
Still another feature of the present invention is associated with an int
Huggins Mark Wayne
Rincon-Mora Gabriel Alfonso
Brady III Wade James
Holmbo Dwight N.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Zweizig Jeffrey
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