High power MOSFET with low on-resistance and high breakdown volt

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357 13, 357 20, 357 41, 357 59, 357 68, 357 91, H01L 2978

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active

043762867

ABSTRACT:
A high power MOSFET is disclosed in which two laterally spaced sources each supply current through respective channels in one surface of a semiconductor chip which are controlled by the same gate. The channels lead from the source electrodes to a relatively low resistivity region and from there to a relatively high resistivity epitaxially formed region which is deposited on a high conductivity substrate. The drain electrode may be either on the opposite surface of the chip or laterally displaced from and on the same side as the source regions. The epitaxially deposited semiconductor material immediately adjacent and beneath the gate and in the path from the sources to the drain has a relatively high conductivity, thereby to substantially reduce the on-resistance of the device without affecting the breakdown voltage of the device. The breakdown voltage of the device is substantially increased by forming a relatively deep p-type diffusion with a large radius in the n-type epitaxial layer beneath each of the sources.

REFERENCES:
patent: 3271640 (1966-09-01), Moore
patent: 3461360 (1969-08-01), Barson et al.
patent: 3909320 (1975-09-01), Cauge et al.
patent: 4072975 (1978-02-01), Ishitani
patent: 4101922 (1978-07-01), Tihanyi et al.
patent: 4145700 (1979-03-01), Jambotkar
patent: 4344081 (1982-08-01), Pao et al.
patent: 4345265 (1982-08-01), Blanchard
I. Yoshida et al., "A High Power MOSFET with a Vertical Drain Electrode and a Meshed Gate Structure," IEEE Journal of Solid-State Circuits, vol. SC-11 #4, Aug. 1976, pp. 472-477.
J. Plummer et al., "A Monolithic 200-V CMOS Analog Switch," IEEE Journal of Solid-State Circuits, vol. SC-11#6, Dec. 1976, pp. 809-817.
B. Scharf et al., "A MOS-Controlled Triac Device," 1978 IEEE International Solid-State Circuits Conference, San Francisco, Calif., Feb. 15-17, 1978, pp. 222-223.
K. Lisiak et al., "Optimization of Non-Planar Power MOS Transistors," IEEE Transactions on Electron Devices, vol. ED-25 #10, Oct. 1978, pp. 1229-1234.
H. Sigg et al., "D-MOS Transistor for Microwave Applications," IEEE Transactions on Electron Devices, vol. ED-19#1, Jan. 1972, pp. 45-53.
R. Cady et al., "Intergration Technique for Closed Field-Effect Transistors," IBM Technical Disclosure Bulletin, vol. 16 #11, Apr. 1974, pp. 3519-3520.
H. Lin et al., "Optimum Load Device for DMOS Integrated Circuits," IEEE Journal of Solid-State Circuits, vol. SC-11 #4, Aug. 1976, pp. 443-452.

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