High power MOS device and fabrication method therefor

Details High power MOS device and fabrication method therefor High power MOS device and fabrication method therefor

1977-04-15

1979-03-20

Wojciechowicz, Edward J.

357 23, 357 54, 357 59, H01L 2906

Patent

active

041457030

ABSTRACT:
This disclosure relates to a high power VMOS semiconductor device and fabrication method therefor. This VMOS semiconductor device uses a doped polysilicon gate electrode in the V groove and an overlying metal electrode located over an insulation layer protecting the doped polysilicon gate electrode. This overlying metal electrode layer covers substantially the entire surface area (except for a small area where electrical contact is made to the doped polysilicon gate electrode) of one surface of the device. Another embodiment discloses the use of a self-aligned metal contact to the source or drain region of the VMOS device between adjacent V grooves.

REFERENCES:
patent: 3798514 (1974-03-01), Hayashi et al.
patent: 3975221 (1976-08-01), Rodgers
patent: 4048649 (1977-09-01), Bohn
patent: 4070690 (1978-01-01), Wickstrom

Affiliated with

Also associated with

Rating

High power MOS device and fabrication method therefor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High power MOS device and fabrication method therefor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High power MOS device and fabrication method therefor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-223831