Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2002-11-20
2004-05-11
Graybill, David E. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S727000, C257S730000, C257S732000, C257S678000, C029S025010, C439S342000, C439S259000, C439S261000, C439S266000, C439S268000
Reexamination Certificate
active
06734548
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a package for a semiconductor device and specifically to a package for semiconductor devices that use a pin grid array.
BACKGROUND OF THE INVENTION
As more and more capability is being designed into semiconductor devices, such as memory modules and microprocessors, there are an increasing number of leads or input/output elements being placed onto electronics packages. In the past, peripherally leaded packages provided an adequate number of leads or input/output elements. Peripherally leaded packages have leads or input/output elements along the edges of the electronic component. In many applications, such packages provide an adequate number of input/output elements. In the past few years, however, many semiconductor devices require more input/output elements than provided in a peripherally leaded package.
To provide additional electrical contacts for a semiconductor device, many have used a grid array package. In a grid array package the input/output elements placed on the surface of the semiconductor devices. The grid array packages have many advantages including simplicity, high contact density, and extremely low inductance due to the short paths between the contact and the element within the semiconductor device. There are several types of grid arrays. Ball grid arrays and chip scale packages have hemispherical solder balls as input/output elements. Pin grid arrays have gold plated pins as input/output elements. Land grid arrays have flat gold plated pads as input/output elements.
In general, the grid array packages are lower cost solutions than the peripherally leaded packages. Of the grid array packages, the most fragile package is the pin grid array package. The pins of the pin grid array package are prone to bending and must be protected once the package is in the socket. Once the pin grid array package is in a position where the pins are protected, the wiping distance must be sufficient to allow for good, reliable electrical contact with each of the pins.
Another problem associated with pin grid array packages is that the pin grid array packages have limited current carrying capability. Currently, the pins of the pin grid array are used either to carry input/output signals or to carry power. Simply put, the capability of the individual pins to carry power is limited due to the small size of the pins which, in turn, limits the amount of power that can be input to a die on such packages. Some electronic devices within the dies now require increased amounts of power. One such electronic device is a microprocessor. It is anticipated that the power requirements will increase further over time. The high current power levels require a larger number of pins. Adding more pins will require a larger substrate area, which is not only costly but also effects thermal and electrical performance. A larger substrate will increase the distance from the pin to the die, which will increase the trace resistance. Higher trace resistance would cause more heating within the substrate and more voltage droop. As a result, there is a need for a package so that the electronic device is not limited by the power-carrying capability associated with the pins.
There is also a growing demand for high loads and evenly distributed loads on a die package. Current pin grid array packages have difficulty in handing a high load and difficulty in distributing the load on the packages evenly. This lacking is yet another technical hurdle associated with pin grid array packages.
Thus, there is a need for a pin grid array packaging method and apparatus that overcomes the limited current carrying capability of the pins of the pin grid array package. There is also a need to assure good, reliable electrical contact between the contacts and the individual pins. There is also a need to meet the demand for high and evenly distributed die loads.
REFERENCES:
patent: 5513076 (1996-04-01), Werther
patent: 5810609 (1998-09-01), Faraci et al.
patent: 5985697 (1999-11-01), Chaney et al.
patent: 6016254 (2000-01-01), Pfaff
Graybill David E.
Intel Corporation
Schwegman Lundberg Woessner & Kluth P.A.
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