High power buffer circuit with low noise

Details High power buffer circuit with low noise High power buffer circuit with low noise

1987-06-05

1989-05-02

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307446, 307451, 307594, 307263, H03K 1716, H03K 19094

Patent

active

048271594

ABSTRACT:
A CMOS output buffer circuit is reduced its output pulse noise and excess current which runs through the CMOS when it is switched ON and OFF. In the gate circuits of p and n channel FETs of the CMOS output buffer circuit, a time constant circuit is inserted. The time constant circuit slightly slows down the voltage variation of input signals to the gates, so the rush current which runs through the output FETs for charging up or discharging the load capacitance is decreased. So, the dI/dt noise is reduced, but the total switching time of the output circuit is not so much affected. By the difference of time lags between the build up and trailing edges of input pulses for both output FETs, one of the output FETs becomes conductive always after the other one is cut off. So, the excess current is reduced. The time constant circuit is composed of a series connected resistor and inverter circuit, connected between positive and negative voltage sources. The time constant circuit many be provided in both or one of the driving circuits for the output FETs. The resistors may be replaced by FETs having proper internal resistances.

REFERENCES:
patent: 4164842 (1979-08-01), Ebihara
patent: 4518873 (1985-05-01), Suzuki et al.
patent: 4567378 (1986-01-01), Raver
patent: 4584491 (1986-04-01), Ulmer
patent: 4587445 (1986-05-01), Kanuma
patent: 4622482 (1986-11-01), Ganger
patent: 4638187 (1987-01-01), Boler et al.
patent: 4672243 (1987-06-01), Kirsch

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