High potential hold circuit

Details High potential hold circuit High potential hold circuit

1986-10-21

1988-05-24

Zazworsky, John

Electrical transmission or interconnection systems

With nonswitching means responsive to external nonelectrical...

Temperature responsive

307353, 307572, H03K 513, H03K 19003, G11C 2702

Patent

active

047468246

ABSTRACT:
This invention provides a high potential hold circuit comprising: a high potential node; a high potential hold enhancement mode MOS transistor for holding a potential of the high potential node by setting the high potential hold transistor in an non-conducting state after the node is charged, having one end connected to a first input signal and the other end connected to the high potential node; a discharge enhancement mode MOS transistor for discharging the potential of the high potential node, having one end connected to the ground potential, the other end connected to the high potential node and a gate connected to a second input signal; a field relaxation enhancement mode MOS transistor located between the high potential node and the high potential hold transistor; and charge-discharge means for charging and discharging a potential of a gate of the field relaxation transistor.

REFERENCES:
patent: 4388538 (1983-06-01), Ikeda
ISSCC 85/Friday, Feb. 15, 1985, Digest of Technical Papers Session XVIII Fam187 Hot-Carrier Suppressed VLSI with Submicron Geometry pp. 272-273.

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