High phase margin low power flip-flop

Details High phase margin low power flip-flop High phase margin low power flip-flop

2000-05-31

2002-09-17

Smith, Matthew (Department: 2825)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S201000

Reexamination Certificate

active

06452433

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to flip-flop circuits. More particularly, the present invention relates to a low power flip-flop having a higher phase margin than conventional flip-flops utilized in digital data recovery circuits.
BACKGROUND OF THE INVENTION
Flip-flop circuits are often utilized in the context of digital data/clock recovery schemes and, particularly, in phase detector arrangements employed in clock recovery circuits. Clock recovery circuits are used to obtain timing information from a digital signal that has been transmitted or communicated without a corresponding clock signal. Consequently, such flip-flop circuits may be used in any number of practical digital applications, e.g., SONET systems, ethernet systems, lightwave communication systems, hard drive reading systems, or the like.
A conventional flip-flop circuit
100
is illustrated in
FIG. 1
as a simple block diagram. Flip-flop circuit
100
generally includes an input data buffer
102
, an input clock buffer
104
, a master latch circuit
106
, and a slave latch circuit
108
. Input buffers may be employed in such a flip-flop circuit because fan-out and slew rate affects the phase margin at high speeds. The basic operations of flip-flops, buffers, and latches are well known to those skilled in the art. Accordingly, such fundamentals are not described in detail herein. In accordance with known principles, flip-flop circuit
100
generates an output
116
of digital bits in response to an input
1
18
of digital bits and in response to a clock signal
109
. Master latch
106
and slave latch
108
sample and hold the digital data in response to a master clock signal
112
and the slave clock signal
114
.
Input data buffer
102
and input clock buffer
104
may function as amplifiers to suitably condition a digital input signal
118
and a digital clock signal
109
, respectively (for purposes of this description, the various input and output signals are assumed to be digital signals). Input data buffer
102
is connected to a master data input of master latch circuit
106
such that the output of input data buffer
102
is associated with a master data input signal
110
. Input clock buffer
104
produces master clock signal
112
(which may include a clock signal and an inverse clock signal), while slave clock signal
114
is in anti-phase with master clock signal
112
. The output of master latch circuit
106
is connected to the data input of slave latch circuit
108
. Slave latch circuit
108
generates output signal
116
in response to slave clock signal
114
. In a practical embodiment, master data input signal
110
, the output of master latch circuit
106
, and output signal
116
are differential signals (the various figures may represent such differential signals with a single line).
FIG. 2
is a timing diagram that illustrates the sample and hold patterns associated with flip-flop circuit
100
. Sample and hold periods for master latch circuit
106
respectively correspond with hold and sample periods for slave latch circuit
108
. In flip-flop circuit
100
, master latch circuit
106
switches from a sampling state to a holding state in response to the falling edge transition of master clock signal
112
. As is well known to those skilled in the art, the differential clock signals enable master latch circuit
106
and slave latch circuit
108
to be clocked out of phase in a practical manner by reversing the positive and negative clock inputs. Similarly, master latch circuit
106
switches from a holding state to a sampling state in response to the rising edge transition of master clock signal
112
. Due to the inverse nature of slave clock signal
114
relative to master clock signal
112
, slave latch circuit
108
switches from a holding state to a sampling state in response to the falling edge transition of master clock signal
112
(i.e., the rising edge transition of slave clock signal
114
) and switches from a sampling state to a holding state in response to the rising edge transition of master clock signal
112
(i.e., the falling edge transition of slave clock signal
114
).
A “centered” setup hold data alignment
120
(for maximum decision margin) and a setup hold data alignment violation
122
are depicted in
FIG. 2
, where it is assumed that the internal flip flop delays are negligible or zero. “DATA
M
IN” represents a stream of digital bits (e.g., bit values A, B, and C, where A, B, and C are either ones or zeros) present at the D input to master latch circuit
106
. “DATA
M
OUT” represents a stream of digital bits present at the Q output of master latch circuit
106
. Similarly, “DATA
S
OUT” represents a stream of digital bits present at the Q output of slave latch circuit
108
. With respect to centered alignment
120
, master latch circuit
106
transitions from sample to hold when the current DATA
M
IN value (bit A) is well settled, i.e., the input to master latch circuit
106
had plenty of time to settle to the current value near the beginning of the sample period. Thus, when slave latch circuit
108
begins sampling bit A, the output value held at master latch circuit
106
is well before the transition clock edge. The master sample to hold (and slave hold to sample) transition point is indicated by the dashed line
124
.
In contrast to centered alignment
120
, alignment violation
122
depicts a situation where flip-flop circuit
100
may encounter errors. A setup hold alignment violation may occur if master latch circuit
106
is changing from the sample state to the hold state while the input data is changing. The transition from master latch sample to master latch hold is indicated by the dashed line
126
. At this time, the current DATA
M
IN value is changing from bit A to bit C. Consequently, the sample to hold transition may encounter a “glitch” because master latch circuit
106
is attempting to hold a bit value that may be changing, which in turn causes the input of slave latch circuit
108
to vary. Such a glitch or imperfection is depicted in the DATA
M
OUT pattern proximate transition point
126
. If the change in the DATA
M
IN bit occurs at (or sufficiently near to) the transition point
126
, then an output bit error may result because, in this example, the DATA
S
OUT bit can either be bit A or bit C. On the other hand, if the change in the DATA
M
IN bit does not occur at the transition point
126
, then an output delay may occur while slave latch circuit
108
waits for the bit value at the output of master latch circuit
106
to stabilize. As the transition point
126
approaches the point where the DATA
M
IN bit value changes, the output delay increases until, eventually, a bit error occurs.
In addition, because both master latch circuit
106
and slave latch circuit
108
can be transparent (i.e., the latch input appears at the latch output) during the transition
126
, the desired output edge of the output signal may be delayed due to finite slew rates. In phase detector applications, where the phase information is typically obtained by comparing the input of the master latch to the retimed data (e.g., the output of the master latch), this delay results in a phase measurement error.
The phase margin of flip-flop circuits can be defined as the phase range between the clock and data that does not cause a significant delay of the output relative to the corresponding delay when the clock and data are “centered” (as described above). The setup time can be defined as the time the necessary for the data to be valid before the clock edge transition point, while the hold time can be defined as the time necessary for the data to be valid after the clock edge transition point. In other words, a flip-flop circuit having a large phase margin is able to process data over a larger phase difference range. For example, an arbitrary failure point for a flip-flop circuit may be defined with respect to the increase in the data zero crossing edge displacement relative to the centered sample condition. This value may be designa

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