Oscillators – With frequency adjusting means – With voltage sensitive capacitor
Patent
1994-12-07
1995-11-21
Mis, David
Oscillators
With frequency adjusting means
With voltage sensitive capacitor
331 8, 331 17, 331 34, 331175, 331 57, 327237, 327270, H03B 504, H03B 524, H03L 100, H03L 7099
Patent
active
054691206
ABSTRACT:
A bias voltage generator for a voltage controlled oscillator is described. In one aspect of the invention, the bias voltage generator includes a biasing circuit to generate a minimum clock output at zero operating voltage, and includes a common mode rejection circuit for the BIASN and BIASP control voltages for the differential delay stages and a IDD test current shut-down circuit. A differential delay stage is described that includes a current source controlled by the BIASN and BIASP control voltages from the bias voltage generator, a resistance linearization circuit for current controlling transistors of a BIASN circuit, and a process variation circuit for compensating for temperature and process variations. The improved characteristics of the resulting VCO permits high frequency operation with a relatively low gain, relatively constant gain throughout operating voltage range, improved noise rejection capabilities, increased speed of delay stage, and reduced output signal swing. All of which contribute to improved phase locked loop reliability especially when operating near the ends of the operating range.
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Nguyen Trung T.
Zhao Jin
LSI Logic Corporation
Mis David
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