Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
2003-10-20
2004-11-30
Nuton, My-Trang (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S096000
Reexamination Certificate
active
06825697
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to electronics. More specifically, the present invention relates to sample and hold circuits.
2. Description of the Related Art
Sample and hold circuits (also known as track and hold circuits) are often used in analog-to-digital conversion. A sample and hold circuit (S/H) follows an analog input signal and, at predetermined intervals, holds the input voltage so that it may be converted to a digital value.
Most traditional sample and hold circuits, such as that described in U.S. Pat. No. 6,028,459, entitled “TRACK AND HOLD CIRCUIT WITH CLAMP,” operate on the concept of injection of additional current at the base of the input transistor of the sampling gate as the circuit switches from track mode to hold. In track mode, the current on the input transistor is equivalent to a unity current (I). In hold mode, however, the current is effectively doubled in the input transistor as a result of the switching in of a separate, larger current source (with amplitude of 2I), resulting in a delta current of amplitude I in the input transistor. This injection of additional current (or delta current) results in an additional distortion mechanism being introduced within the signal path, and thus deterioration in the spectral purity of the track and hold output.
The effect on the degradation of the spectral purity can be addressed. As a result of the switching action, the current in the input transistor changes from 2I to I when the S/H goes from hold to track. This produces a base current step transient that must settle into the input filter thereby degrading the acquisition settling time of the gate. Additionally, the current transient in the input transistor as a result of the discharging of the transistor further degrades the acquisition settling performance. For the track-to-hold transition, the current settling response will affect the hold mode performance at the hold capacitor as a result of the finite isolation of the sampling gate in bold mode: In order to improve both the track mode and hold mode performance, the current in the input transistor should remain constant.
U.S. Pat. No. 5,457,418, entitled “TRACK AND HOLD CIRCUIT WITH AN INPUT TRANSISTOR HELD ON DURING HOLD MODE,” discloses a sample and hold circuit in which the current does not double in the input transistor. However, the current is switched from one differential pair to another, creating an unwanted transient similar to that described above due to the finite delays associated with the switching times of the differential pairs.
Hence, there is a need in the art for an improved system or method for sampling and holding a signal, which reduces the current transients in the input transistor.
SUMMARY OF THE INVENTION
The need in the art is addressed by the system and method for sampling and holding a signal of the present invention. The invention includes a novel input circuit for a track and hold circuit comprising a circuit for receiving an input signal including an input node, a first output node N
1
, and a path connecting the input and output nodes; a current switching circuit for applying a first current to the node N
1
during a first mode of operation but not during a second mode; and a current source for applying a second current to the node N
1
during both of the first and second modes. The value of the first current is determined such that the total current in the path is constant during the first and second modes. In an illustrative embodiment, the first mode is a track mode and the second mode is a hold mode.
REFERENCES:
patent: 4806790 (1989-02-01), Sone
patent: 5004935 (1991-04-01), Murayama et al.
patent: 5315170 (1994-05-01), Vinn et al.
patent: 5457418 (1995-10-01), Chang
patent: 5583459 (1996-12-01), Sone
patent: 6028459 (2000-02-01), Birdsall et al.
patent: 6127856 (2000-10-01), Ueda
patent: 6262677 (2001-07-01), Kiriaki et al.
Devendorf Don C.
Hirata Erick M.
Linder Lloyd F.
Nuton My-Trang
Telasic Communications, Inc.
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