High-performance thin-film transistor and SRAM memory cell

Details High-performance thin-film transistor and SRAM memory cell High-performance thin-film transistor and SRAM memory cell

1995-05-31

1996-10-22

Limanek, Robert P.

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Field effect device in non-single crystal, or...

257903, 257622, 257330, 257350, H01L 2978

Patent

active

055679587

ABSTRACT:
A thin-film transistor and SRAM memory cell include thin-film source and drain regions (12, 14) separated by an opening (22) and overlying and insulating layer (11). A thin-film channel layer (16) overlies the thin-film source and drain regions (12, 14) and a portion of the insulating layer (11) exposed by the opening (22). A thin-film gate electrode (20) is positioned in the opening (22) and defines a thin-film channel region (24) in the thin-film channel layer (16). The thin-film gate electrode (20) is separated from the thin-film channel region (24) by a gate dielectric layer (18). The thin-film channel region (24) extends along vertical wall surfaces (26, 28) of the thin-film source and drain regions (12, 14) providing an extended channel length for the thin-film transistor.

REFERENCES:
patent: 4845537 (1989-07-01), Nishimura et al.
patent: 4864374 (1989-09-01), Banerjee
patent: 5124768 (1992-06-01), Mano et al.
patent: 5208476 (1993-05-01), Inoue
patent: 5404030 (1995-04-01), Kim et al.
patent: 5407846 (1995-04-01), Chan
H. Kuriyama et al., "An Asymmetric Memory Cell using a C-TFT for ULSI SRAMs", 1992 Symposium on VLSI Technology Digest of Tech.Papers, pp. 38-39 .

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