Electrical computers and digital processing systems: processing – Processing architecture – Superscalar
Patent
1998-09-10
1999-10-05
Pam, Daniel H.
Electrical computers and digital processing systems: processing
Processing architecture
Superscalar
712 25, 712215, 710 56, G06F 930, G06F 938, G06F 928
Patent
active
059616296
ABSTRACT:
A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instructions in-order.
REFERENCES:
patent: 3346851 (1967-10-01), Thornton et al.
patent: 3771138 (1973-11-01), Celtruda et al.
patent: 3789365 (1974-01-01), Jen et al.
patent: 4034349 (1977-07-01), Monaco et al.
patent: 4200927 (1980-04-01), Hughes et al.
patent: 4228495 (1980-10-01), Bernhard et al.
patent: 4296470 (1981-10-01), Fairchild et al.
patent: 4315314 (1982-02-01), Russo
patent: 4410939 (1983-10-01), Kawakami
patent: 4434461 (1984-02-01), Puhl
patent: 4459657 (1984-07-01), Murao
patent: 4476525 (1984-10-01), Ishii
patent: 4626989 (1986-12-01), Torii
patent: 4675806 (1987-06-01), Uchida
patent: 4714994 (1987-12-01), Oklobdzija et al.
patent: 4722049 (1988-01-01), Lahti
patent: 4752873 (1988-06-01), Shonai et al.
patent: 4758948 (1988-07-01), May et al.
patent: 4766566 (1988-08-01), Chuang
patent: 4807115 (1989-02-01), Torng
patent: 4858105 (1989-08-01), Kuriyama et al.
patent: 4897810 (1990-01-01), Nix
patent: 4901228 (1990-02-01), Kodama
patent: 4903196 (1990-02-01), Pomerene et al.
patent: 4924376 (1990-05-01), Ooi
patent: 4926323 (1990-05-01), Baror et al.
patent: 4942525 (1990-07-01), Shintani et al.
patent: 4985825 (1991-01-01), Webb, Jr. et al.
patent: 4992938 (1991-02-01), Coke et al.
patent: 5003462 (1991-03-01), Blaner et al.
patent: 5101341 (1992-03-01), Circella et al.
patent: 5226126 (1993-07-01), McFarland et al.
patent: 5226170 (1993-07-01), Rubinfeld
patent: 5230068 (1993-07-01), Van Dyke et al.
patent: 5355460 (1994-10-01), Eickenmeyer et al.
patent: 5442757 (1995-08-01), McFarland et al.
patent: 5487156 (1996-01-01), Popescu et al.
patent: 5539911 (1996-07-01), Nguyen et al.
patent: 5561776 (1996-10-01), Popescu et al.
patent: 5574927 (1996-11-01), Scantlin
patent: 5592636 (1997-01-01), Popescu et al.
patent: 5625837 (1997-04-01), Popescu et al.
patent: 5627983 (1997-05-01), Popescu et al.
patent: 5651125 (1997-07-01), Witt et al.
patent: 5689720 (1997-11-01), Nguyen et al.
patent: 5708841 (1998-01-01), Popescu et al.
patent: 5768575 (1998-06-01), McFarland et al.
patent: 5778210 (1998-07-01), Henstrom et al.
patent: 5797025 (1998-08-01), Popescu et al.
patent: 5832205 (1998-11-01), Kelly et al.
patent: 5832293 (1998-11-01), Popescu et al.
Smith, M.D. et al., "Boosting Beyond Static Scheduling in a Superscalar Processor," IEEE, 1990, pp. 344-354.
Murakami, K. et al., "SIMP (Single Instruction stream/Multiple instruction Pipelining): A Novel High-Speed Single-Processor Architecture,"ACM, 1989, pp. 78-85.
Jouppi, N.P., "The Nonuniform Distribution of Instruction-Level and Machine Parallelism and Its Effect on Performance," IEEE Transactions on Computers, vol. 38, No. 12, Dec. 1989, pp. 1645-1658.
Horst, R.W. et al., "Multiple Instruction Issue in the NonStop Cyclone Processor," IEEE, 1990, pp. 216-226.
Goodman, J.R. and Hsu, W., "Code Scheduling and Register Allocation in Large Basic Blocks," ACM, 1988, pp. 442-452.
Lam, M.S., "Instruction Scheduling For Superscalar Architectures," Ann. Rev. Comput. Sci., vol. 4, 1990, pp. 173-201.
Aiken, A. and Nicolau, A., "Perfect Pipelining: A New Loop Parallelization Technique*," pp. 221-235.
Jouppi, N.H., "Integration and Packaging Plateaus of Processor Performance," IEEE, 1989, pp. 229-232.
Groves, R.D. and Oehler, R., "An IBM Second Generation RISC Processor Architecture," IEEE, 1989, pp. 134-137.
H. B. Bakoglu et al., "IBM Second-Generation RISC Machine Organization", 1990 IEEE, pp. 173-178.
S. McGeady, "The i960CA Superscalar Implementation of the 80960 Architecture", 1990 IEEE, pp. 232-240.
H. Nakano et al., "A 80 Mflops 64-bit Microprocessor for Parallel Computer", 1991 IEEE, pp. 15.2.1-15.2.4.
Andrews, Distinctions Blur Between DSP Solutions, Computer Design, vol. 28, No. 9, May 1, 1989, Littleton, Mass., pp. 86-99.
Colwell et al., A VLIW Architecture for a Trace Scheduling Compiler, Proceedings of the 2.sup.nd International Conference on Architectural Support for Programming Languages and Operating Systems, Oct. 5-8, 1987, California.
Hennessy et al., Computer Architecture: A Quantitative Approach, Morgan Kaufmann Publishers, Inc., 1990 (in its entirety).
IBM Technical Disclosure Bulletin, Overlap of Store Multiple Operation With Succeeding Operations Through Second Set of General Purpose Registers, vol. 28, No. 6, Nov. 1989, New York, NY, pp. 2727-2728.
Jelemensky, New Microcomputer Features Advanced Hardware For Real-Time Control Applications, Electro Conference Record, vol. 14, Apr. 11, 1989, Los Angeles, CA, pp. 511-519.
Johnson, Superscalar Microprocessor Design, Prentice-Hall, Inc., 1991 (in its entirety).
Melear, C., Motorola, Inc., The Design of the 88000 RISC Family, IEEE Micro, vol. 9, No. 2, Apr. 1989, Los Alamitos, CA, pp. 26-38.
Patent Abstracts of Japan, vol. 010, No. 089, Apr. 1986, & JP, A, 60 225 943 (Hitachi Seisakusho K K) Nov. 11, 1985.
Popescu et al., The Metaflow Architecture, Metaflow Technologies, Inc., Jun., 1991 (in its entirety).
Smith et al., Implementing Precise Interrupts in Pipelined Processors, IEEE Transactions On Computers, vol. 37, No. 5, May 1988, New York, NY, pp. 562,573.
Weiss, R., Third-Generation RISC Processors, On Special Report, Mar. 30, 1992, pp. 96-108.
"The Single Component MCS.RTM.-48 System", 8-bit Embedded Controller Handbook, Intel, 1989.
Lee, Ruby B., "Precision Architecture", Computer, Jan. 1989, pp. 78-91.
Odnert et al., "Architecture and Compiler Enhancements for PA-RISC Workstations", Proceedings from IEEE Compcon, Feb. 1991, San Francisco, CA, pp. 214-218.
Smith et al., "Implementation of Precise Interrupts in Pipelined Processors," Proceedings of the 12th Annual International Symposium on Computer Architecture, Jun. 1985, pp. 36-44.
Wedig, R.G., Detection of Concurrency In Directly Executed Language Instruction Streams, (Dissertation), Jun. 1982, pp. 1-179.
Agerwala et al., "High Performance Reduced Instruction Set Processors," IBM Research Division, Mar. 31, 1987, pp. 1-61.
Gross et al., "Optimizing Delayed Branches," Proceedings of the 5th Annual Workshop on Microprogramming, Oct. 5-7, 1982, pp. 114-120.
Tjaden et al., "Representation of Concurrency with Ordering Matrices," IEEE Trans. On Computers, vol. C-22, No. 8, Aug. 1973, pp. 752-761.
Tjaden, Representation and Detection of Concurrency Using Ordering Matrices, (Dissertation), 1972, pp. 1-199.
Foster et al., "Percolation of Code to Enhance Parallel Dispatching and Execution," IEEE Trans. On Computers, Dec. 1971, pp. 1411-1415.
Thornton, J.E., Design of a Computer: The Control Data 6600, Control Data Corporation, 1970, pp. 58-140.
Weiss et al., "Instruction Issue Logic in Pipelined Supercomputers," Reprinted from IEEE Trans. On Computers, vol. C-33, No. 11, Nov. 1984, pp. 1013-1022.
Tomasulo, R.M., "An Efficient Algorithm for Exploiting Multiple Arithmetic Units," IBM Journal, vol. 11, Jan. 1967, pp. 25-33.
Tjaden et al., "Detection and Parallel Execution of Independent Instructions," IEEE Trans. On Computers, vol. C-19, No. 10, Oct. 1970, pp. 889-895.
Smith et al., "Limits on Multiple Instruction Issue," Proceedings of the 3rd International Conference on Architectural Support for Programming Languages and Operating Systems, Apr. 1989, pp. 290-302.
Pleszkun et al., "The Performance Potential of Multiple Functional
Garg Sanjiv
Hagiwara Yasuaki
Lau Te-Li
Lentz Derek J.
Miyayama Yoshiyuki
Pam Daniel H.
Seiko Epson Corporation
LandOfFree
High performance, superscalar-based computer system with out-of- does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High performance, superscalar-based computer system with out-of-, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High performance, superscalar-based computer system with out-of- will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1165383