Patent
1992-01-08
1996-07-23
Teska, Kevin J.
G06F 1300
Patent
active
055399118
ABSTRACT:
A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches and stores program instruction sets. Each instruction set includes a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instruction sets and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers which are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instructions in-order.
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Garg Sanjiv
Hagiwara Yasuaki
Lau Te-Li
Lentz Derek J.
Miyayama Yoshiyuki
Fiul Dan
Seiko Epson Corporation
Teska Kevin J.
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