High performance superscalar alignment unit

Details High performance superscalar alignment unit High performance superscalar alignment unit

1997-10-03

1998-11-03

Lall, Parshotam S.

395391, G06F 938

Patent

active

058322493

ABSTRACT:
An instruction alignment unit is provided which is capable of routing variable byte length instructions simultaneously to a plurality of decode units which form fixed issue positions within a superscalar microprocessor. The instruction alignment unit may be implemented with a relatively small number of cascaded levels of logic gates, thus accomodating very high frequencies of operation. In none embodiment, the superscalar microprocessor includes an instruction cache for storing a plurality of variable byte-length instructions and a predecode unit for generating predecode tags which identify the location of the start byte of each variable byte-length instruction. An instruction alignment unit is configured to channel a plurality of the variable byte-length instructions simultaneously to predetermined issue positions depending upon the locations of their corresponding start bytes in a cache line. The issue position or positions to which an instruction may be dispatched is limited depending upon the position of the instruction's start byte within a line. By limiting the number of issue positions to which a given instruction within a line may be dispatched, the number of cascaded levels of logic required to implement the instruction alignment unit may be advantageously reduced.

REFERENCES:
patent: 4044338 (1977-08-01), Wolf
patent: 4453212 (1984-06-01), Gaither et al.
patent: 4807115 (1989-02-01), Torng
patent: 4858105 (1989-08-01), Kuriyama et al.
patent: 5113515 (1992-05-01), Fite et al.
patent: 5179671 (1993-01-01), Kelly et al.
patent: 5226126 (1993-07-01), McFarland et al.
patent: 5226130 (1993-07-01), Favor et al.
patent: 5438668 (1995-08-01), Coon et al.
patent: 5442760 (1995-08-01), Rustad et al.
patent: 5450605 (1995-09-01), Grochowski et al.
patent: 5463748 (1995-10-01), Schwendinger
patent: 5535347 (1996-07-01), Grochowski et al.
patent: 5537629 (1996-07-01), Brown et al.
Intel, "Chapter 2: Microprocessor Architecture Overview," pp. 2-1 through 2-4.
Michael Slater, "AMD's K5 Designed to Outrun Pentium," Microprocessor Report, vol. 8, No. 14, Oct. 24, 1994, 7 pages.
Sebastian Rupley and John Clyman, "P6: The Next Step?,"PC Magazine, Sep. 12, 1995, 16 pages.
Tom R. Halfhill, "AMD K6 Takes On Intel P6," BYTE, Jan. 1996, 4 pages.

Affiliated with

Also associated with

Rating

High performance superscalar alignment unit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High performance superscalar alignment unit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High performance superscalar alignment unit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-701410