High performance strained CMOS devices

Details High performance strained CMOS devices High performance strained CMOS devices

2007-04-17

2007-04-17

Lebentritt, Michael (Department: 2812)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C257SE21549

Reexamination Certificate

active

11060784

ABSTRACT:
A semiconductor device and method of manufacture provide an n-channel field effect transistor (nFET) having a shallow trench isolation with overhangs that overhang Si—SiO2interfaces in a direction parallel to the direction of current flow and in a direction transverse to current flow. The device and method also provide a p-channel field effect transistor (pFET) having a shallow trench isolation with an overhang that overhangs Si—SiO2interfaces in a direction transverse to current flow. However, the shallow trench isolation for the pFET is devoid of overhangs, in the direction parallel to the direction of current flow.

REFERENCES:
patent: 5395790 (1995-03-01), Lur
patent: 5834358 (1998-11-01), Pan et al.
patent: 5940716 (1999-08-01), Jin et al.
patent: 5953621 (1999-09-01), Gonzalez et al.
patent: 5960297 (1999-09-01), Saki
patent: 5963819 (1999-10-01), Lan
patent: 5976948 (1999-11-01), Werner et al.
patent: 5981356 (1999-11-01), Hsueh et al.
patent: 6022781 (2000-02-01), Noble et al.
patent: 6080637 (2000-06-01), Huang et al.
patent: 6093621 (2000-07-01), Tseng
patent: 6097076 (2000-08-01), Gonzalez et al.
patent: 6271143 (2001-08-01), Mendicino
patent: 6271147 (2001-08-01), Tseng
patent: 6316815 (2001-11-01), Tseng
patent: 6368973 (2002-04-01), Tseng
patent: 6417072 (2002-07-01), Coronel et al.
patent: 6483171 (2002-11-01), Forbes et al.
patent: 6566207 (2003-05-01), Park
patent: 6566225 (2003-05-01), Lai et al.
patent: 6583060 (2003-06-01), Trivedi
patent: 6717216 (2004-04-01), Doris et al.
patent: 6825529 (2004-11-01), Chidambarrao et al.
patent: 6831292 (2004-12-01), Currie et al.
patent: 6955955 (2005-10-01), Chen et al.
patent: 6974981 (2005-12-01), Chidambarrao et al.
patent: 6977194 (2005-12-01), Belyansky et al.
patent: 7015082 (2006-03-01), Doris et al.
patent: 2002/0063292 (2002-05-01), Armstrong et al.
patent: 2003/0032261 (2003-02-01), Yeh et al.
patent: 2003/0040158 (2003-02-01), Saitoh
patent: 2004/0238914 (2004-12-01), Deshpande et al.
patent: 2004/0262784 (2004-12-01), Doris et al.
patent: 2005/0040460 (2005-02-01), Chidambarrao et al.
patent: 2005/0082634 (2005-04-01), Doris et al.
patent: 2005/0093030 (2005-05-01), Doris et al.
patent: 2005/0098829 (2005-05-01), Doris et al.
patent: 2005/0106799 (2005-05-01), Doris et al.
patent: 2005/0145937 (2005-07-01), Chen et al.
patent: 2005/0145954 (2005-07-01), Zhu et al.
patent: 2005/0148146 (2005-07-01), Doris et al.
patent: 2005/0194699 (2005-09-01), Belyansky et al.
patent: 2005/0236668 (2005-10-01), Zhu et al.
patent: 2005/0245017 (2005-11-01), Belyansky et al.
patent: 2005/0280051 (2005-12-01), Chidambarrao et al.
patent: 2005/0282325 (2005-12-01), Belyansky et al.
patent: 2006/0008971 (2006-01-01), Park
patent: 2006/0027868 (2006-02-01), Doris et al.
patent: 2006/0057787 (2006-03-01), Doris et al.
patent: 2006/0060925 (2006-03-01), Doris et al.
patent: 64-76755 (1989-03-01), None
G. Zhang, et al., “A New ‘Mixed-Mode’ Reliability Degradation Mechanism in Advanced Si and SiGe Bipolar Transistors,” IEEE Transactions on Electron Devices, vol. 49, No. 12, Dec. 12, 2002, pp. 2151-2156.
H.S. Momose, et al., “Temperature Dependence of Emitter-Base Reverse Stress Degradation and its Mechanism Analyzed by MOS Structures.” 1989 IEEE, Paper 6.2, pp. 140-143.
C.J. Huang, et al., “Temperature Dependence and Post-Stress Recovery of Hot Electron Degradation Effects in Bipolar Transistors.” IEEE 1991, Bipolar Circuits and Technology Meeting 7.5, pp. 170-173.
S.R. Sheng, et al., “Degradation and Recovery of SiGe HBTs Following Radiation and Hot-Carrier Stressing.” pp. 14-15.
Z. Yang, et al., “Avalanche Current Induced Hot Carrier Degradation in 200 GHz SiGe Heterojunction Bipolar Transistors.” pp. 1-5.
H. Li, et al., “Design of W-Band VCOs with High Output Power for Potential Application in 77 GHz Automotive Radar Systems.” 2003, IEEE GaAs Digest, pp. 263-266.
H. Wurzer, et al., “Annealing of Degraded non-Transistors-Mechanisms and Modeling.” IEEE Transactions on Electron Devices, vol. 41, No. 4, Apr. 1994, pp. 533-538.
B. Doyle, et al., “Recovery of Hot-Carrier Damage in Reoxidized Nitrided Oxide MOSFETs.” IEEE Electron Device Letters, vol. 13. No. 1, Jan. 1992, pp. 38-40.
H.S. Momose, et al. “Analysis of the Temperature Dependence of Hot-Carrier-Induced Degradation in Bipolar Transistors for Bi-CMOS.” IEEE Transactions on Electron Devices, vol. 41, No. 6, Jun. 1994, pp. 978-987.
M. Khater, et al., “SiGe HBT Technology with Fmax/Ft =350/300 GHz and Gate Delay Below 3.3 ps”. 2004 IEEE, 4 pages.
J.C. Bean, et al., “GEx SI 1-x/Si Strained-Layer Superlattice Grown by Molecular Beam Epitaxy”. J. Vac. Sci. Technol. A 2(2), Apr.-Jun. 1984, pp. 436-440.
J.H. Van Der Merwe, “Regular Articles”. Journal of Applied Physics, vol. 34, No. 1, Jan. 1963, pp. 117-122.
J.W. Matthews, et al., “Defects in Epitaxial Multilayers”. Journal of Crystal Growth 27 (1974), pp. 118-125.
Subramanian S. Iyer, et al. “Heterojuction Bipolar Transistors Using Si-Ge Alloys”. IEEE Transactions on Electron Devices, vol. 36, No. 10, Oct. 1989, pp. 2043-2064.
R.H.M. Van De Leur, et al., “Critical Thickness for Pseudomorphic Growth of Si/Ge Alloys and Superlattices”. J. Appl. Phys. 64 (6), Sep. 15, 1988, pp. 3043-3050.
D.C. Houghton, et al., “Equilibrium Critical Thickness for SI 1-x GEx Strained Layers on (100) Si”. Appl. Phys. Lett. 56 (5), Jan. 29, 1990, pp. 460-462.
Q. Quyang et al., “Two-Dimensional Bandgap Engineering in a Novel Si/SiGe pMOSFET with Enhanced Device Performance and Scalability”. 2000, IEEE, pp. 151-154.

Affiliated with

Also associated with

Rating

High performance strained CMOS devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High performance strained CMOS devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High performance strained CMOS devices will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3785584