High performance SRAM device and method of powering-down the...

Details High performance SRAM device and method of powering-down the... High performance SRAM device and method of powering-down the...

2005-07-26

2005-07-26

Phung, Ahn (Department: 2824)

Static information storage and retrieval

Powering

C365S227000, C365S229000

Reexamination Certificate

active

06922370

ABSTRACT:
An SRAM device and a method of powering-down an SRAM device. In one embodiment, the SRAM device includes (1) an SRAM array coupled to an SRAM array low voltage source that provides a low SRAM array supply voltage VSBto the SRAM device and (2) main column peripheral circuitry having main pre-charge circuitry free of an SRAM header, coupled to the SRAM array by bit lines and coupled to a sleep mode controller through an associated main column peripheral driving circuitry that is configured to isolate the bit lines from a power supply during a sleep mode.

REFERENCES:
patent: 5563839 (1996-10-01), Herdt et al.
patent: 5969995 (1999-10-01), Morishima
patent: 6307803 (2001-10-01), Chien
patent: 6839299 (2005-01-01), Bhavnagarwala et al.

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