Patent
1983-11-08
1986-10-28
James, Andrew J.
357 237, 357 4, 357 2, H01L 2978
Patent
active
046202080
ABSTRACT:
A high performance, small area thin film transistor has a drain region, an insulating layer, and a source region at least portions of the edge of which form a non-coplanar surface with respect to a substrate. The insulative layer is formed in between the source and drain regions. A deposited semiconductor overlies the non-coplanar surface to form a current conduction channel between the drain and source. A gate insulator and gate electrode overly at least a portion of the deposited semiconductor adjacent thereto. The length of the current conduction channel is determined by the thickness of the insulative layer and therefore can be made short without precision photolithography. The non-coplanar surface can be formed by utilizing a dry process to simultaneously etch through several layers in a continuous one-step process. A second dielectric layer may be formed above the three previous layers. This decouples the gate electrode from the source region by creating two capacitances in series, thereby limiting further the capacitance between the gate electrode and the source region.
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Fritzsche Hellmut
Johnson Robert R.
Energy Conversion Devices Inc.
Gray, Jr. Richard O.
James Andrew J.
Mintel William
Nolan Robert S.
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