High performance single port RAM generator architecture

Details High performance single port RAM generator architecture High performance single port RAM generator architecture

1995-11-27

1997-12-30

Popek, Joseph A.

Electric lamp and discharge devices: systems

Periodic switch in the supply circuit

Plural load device systems

365204, G11C 700

Patent

active

057038210

ABSTRACT:
A single-port RAM generator architecture, for the generation of different RAM structures in a CAD environment, and to test the operation capabilities of the different RAM structure, The architecture includes a Static RAM matrix and a self timed architecture, which includes a control logic, both a dummy row and a dummy column having respectively equivalent load of a word line and of bit column of said matrix. The dummy column is discharged at a faster rate than the corresponding bit column optimizing the timing and reducing power consumption. Different column multiplexer selections provide different RAMs for a selected RAM size, each having slightly different silicon area and timing performance.

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IBM Technical Disclosure Bulletin, vol. 31, No. 6, Nov. 1988, New York, US, pp. 128-129, "CMOS High Performance Sense Scheme For Growable Macros".
Tou, Jarvis et al., "A Sub-Micron CMOS Embedded SRAM Compiler", IEEE 1991 Integrated Circuits Conference.
Dao, Tim et al., "A Dual-Port SRAM Compiler for 0.8mm 100K BICMOS Gate Arrays", IEEE 1991 Integrated Circuits Conference.

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