Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Reexamination Certificate
1999-08-26
2001-05-15
Jeanpierre, Peguy (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
C341S144000
Reexamination Certificate
active
06232901
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to the field of analog-to-digital and digital-to-analog converters, and particularly to sigma-delta-sigma low-pass/band-pass modulator based analog-to-digital and digital-to-analog converters.
BACKGROUND OF THE INVENTION
High performance analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), preferably covering radio frequency carriers directly, can be utilized in communications equipment. Accordingly, there lies a need for frequency and bandwidth tunable ADCs and DACs.
Referring now to
FIG. 1
, a four-stage sigma-delta-sigma modulator based ADC architecture, which has primarily a low-pass noise-shaping characteristic (i.e., one side of the signal pass band is at DC, and the noise is pushed to frequencies above the highest signal pass band frequency). In each stage of ADC modulator
100
, there are 2 sample and hold circuits
110
and
112
used to delay the stage output by one sample clock period and combine it with the stage input, thereby producing a sampled analog integrator. The system of ADC modulator
100
uses discrete time, rather than continuous time integration, for optimum performance in higher order modulators. The modulator loop delay on noise is minimized, thereby allowing for stable operation using higher effective modulator loop gain than would be possible using continuous time integration (particularly in 1-bit output modulators). Using dual latches
114
and
116
after quantizer
118
minimizes the feedback transient responses of DACs
120
and
134
and consequently the stage output transient responses. An isolated critical first stage DAC
120
is shown to minimize undesired stage to stage interaction via feedback path
122
. De-multiplexer
124
in one embodiment provides optional serial-to-parallel conversion to reduce the physical data rate where needed (i.e., reduce the data bus rate between the modulator and decimator circuits). The “Gx” and “
1
-Gx” gain controls G
1
, G
2
, G
3
,
1
-G
1
,
1
-G
2
, and
1
-G
3
are used to stabilize ADC modulator
100
, while at the same time maintaining a flat response to modulator input
126
at modulator data output
128
. The C
1
and C
2
inputs are non-overlapping, two phase sample clocks used to control the timing of the delay elements (i.e., “S/H pairs” and “latch pairs”). The first two stages
130
and
132
of ADC modulator
100
have a feedback gain control term T
2
which is used to form a partial resonator at the upper frequency end of the pass band, and thereby effectively increase the pass bandwidth. In effect, part of the high frequency pass band noise is moved to the lower frequencies, which flattens and widens the pass band noise response.
Referring now to
FIG. 2
, a linearized model of the sigma-delta-sigma modulator shown in
FIG. 1
will be discussed.
FIG. 2
illustrates how the transfer function of ADC modulator
200
behaves relative to input signal X at input
210
and the quantizer noise Q
N
. Similar linearized models can be formed and transfer equations derived for other numbers of stages.
T feedback terms can be used around all of the paired sets of stages, thereby mostly eliminating the low-pass noise response and replacing it with a tunable band-pass response. In other words, the noise is moved out of the desired signal bandwidth that is center frequency tunable up in frequency. A decimation circuit that would be used to recover the desired resolution and reduce the sample rate would in effect utilize tunable digital frequency translation of the signal bandwidth and a fixed digital filter. When ADC modulator
200
is used as a tunable band-pass ADC, the quality factor “Q” (the ratio of the tune frequency to the signal bandwidth) is not constant, but rather decreases as the tune frequency increases. This is not a problem when the tune frequency is low relative to the modulator sample rate, which is the case when used to enhance the low-pass signal bandwidth. However, as the tune frequency approaches the Nyquist rate (F
S
/2), the noise shaping ability degrades substantially. Thus, there lies a need for a new architecture for a sigma-delta-sigma modulator variation that can provide tunable band-pass performance with constant Q over the sampling band. In such a modulator the noise shaping performance would preferably be basically the same regardless of the tune frequency.
SUMMARY OF THE INVENTION
The present invention is in one embodiment primarily, but not exclusively, directed to an analog-to-digital converter. In one embodiment, the analog-to-digital converter includes at least two or more tunable band-pass filter stages, a first stage of the at least two or more tunable band-pass filter stages receiving an analog input signal and having an output provided to an input of a second stage of the at least two or more band-pass filter stages, a first gain element coupled between the first stage and the second stage for providing a first gain level, a second gain element coupled between the input of the first stage and the input of the second stage for providing a second gain level, and a feedback loop for providing a quantized, delayed and converted to analog version of an output of the second stage to each of the at least two or more tunable band-pass filter stages wherein each of the at least two or more tunable band-pass filter stages is tunable to a respective predetermined frequency.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention and together with the general description, serve to explain the principles of the invention.
REFERENCES:
patent: 5654711 (1997-08-01), Fujimori
patent: 5682161 (1997-10-01), Ribner et al.
patent: 5757301 (1998-05-01), Kuo et al.
patent: 6061008 (2000-05-01), Abbey
Eppele Kyle
Jean-Pierre Peguy
Jensen Nathan O.
O'Shaughnessy J. P.
Rockwell Collins, Inc.
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