High performance semiconductor memory device with low power...

Details High performance semiconductor memory device with low power... High performance semiconductor memory device with low power...

2000-12-21

2001-10-23

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S154000

Reexamination Certificate

active

06307805

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having high density and capability of high performance at low supply voltage.
2. Description of the Related Art
In electronic systems, power consumption is one of the factors determining efficiency and functionality of the system. With the proliferation of wireless and portable electronic devices such as palm top computers, cellular telephones, etc., power consumption has become an important factor to be considered in designing and manufacturing such electronic devices. This is because the portable electronic devices are typically subject to the limitation of battery lifetime, i.e., a duration of usage of a battery between charges. Thus, in battery operated portable electronic devices, there have been efforts to reduce the power consumption of the devices which is an important factor determining the battery lifetime.
For semiconductor memories to be used in the electronic devices, complementary metal oxide silicon (CMOS) technology is most commonly used. Compared with other types of memory cells, CMOS memory cells have a considerable advantage in being much lower in the power consumption. This lower power consumption is due to the fact that either the NMOS or the PMOS transistor of a single CMOS gate in a CMOS memory cell is always off so that there is ideally no direct power drain in the standby mode of the memory cell.
In the technology of CMOS memories, a typical method of reducing the power consumption is lowering a supply voltage for the memories. By lowering the supply voltage, however, operating speed of the memories is degraded such that memory access speed slows down. Such a degradation in the operation speed may be improved by reducing the threshold voltage of the transistors in the memories. In this case, however, the reduction of the threshold voltage causes an increase in subthreshold leakage current of the transistors. The power dissipation due to the subthreshold leakage current is not negligible and affects (i.e., shortens) the battery lifetime.
To overcome these drawbacks, for example, a theory of reducing power consumption of static memories by using multi-threshold voltage CMOS (MTCMOS) technique is disclosed in “1-V, 10-MHz, 3.5-mW, 1-Mb MTCMOS SRAM with Charge-Recycling Input/Output Buffers”, by Shibata et al., June 1999, IEEE Journal of Solid-State Circuits, Vol. 34, No. 6, pp. 866-877. Shibata et al. disclose a six-transistor-type CMOS memory cell which is made up of high-threshold voltage MOSFET's in order to suppress the power dissipation due to larger subthreshold leakage current. The leakage current in each logic gate of a memory cell is reduced by the high-threshold voltage transistors which are cut off during the standby mode. However, a memory cell having pass transistors with the high-threshold voltage has such problems as described below in detail.
Referring to
FIG. 1
, there is provided a circuit diagram illustrating a conventional SRAM cell formed using the MTCMOS technique. The SRAM cell
10
has two pass transistors T
11
, T
12
and two CMOS inverters
12
,
14
each of which has a PMOS transistor and an NMOS transistor. In the SRAM cell
10
, to prevent subthreshold leakage current which occurs during the standby mode, transistors with a high-threshold voltage are used for all the six transistors including the pass transistors T
11
, T
12
. It is well known that MOS transistors with the high-threshold voltage have much less subthreshold leakage current than MOS transistors with a low-threshold voltage. Thus, the subthreshold leakage current can be substantially prevented by using the MOS transistors with the high-threshold voltage for the pass transistors T
11
, T
12
.
As a result, however, the performance of the SRAM cell
10
is significantly affected by the high-threshold voltage pass transistors T
11
, T
12
. For example, the use of the high-threshold voltage transistors T
11
, T
12
may cause a decrease in the read/write operation of the SRAM cell. This is because a high-threshold voltage transistor takes longer time than a low-threshold voltage transistor in processing an input signal. In other words, since the operation speed of a transistor is proportional to the difference between a supply voltage and a threshold voltage of the transistor, the signal processing in a high-threshold transistor is slower than that in a low-threshold voltage transistor.
Furthermore, in order for the SRAM cell
10
to operate stably, the pass transistors T
11
, T
12
should have weaker strength than pull-down NMOS transistors T
13
, T
14
in the CMOS inverters
12
,
14
. In other words, the pull-down NMOS transistors T
13
, T
14
should have a large size enough to maintain the stable operation of the SRAM cell
10
, or the two pass transistors T
11
, T
12
should be very small. However, small pass transistors can significantly reduce the read/write operation speed of the SRAM cell. Thus, the size of the SRAM cell
10
cannot be optimally minimized due to such a difficulty to maintain a reasonable “beta ratio” between the two pass transistors T
11
, T
12
and the pull-down NMOS transistors T
13
, T
14
.
Therefore, a need exists for a CMOS memory cell of which access operation can be performed at high speed and with lower power consumption. Further, it is desirable that the CMOS memory cell has a minimum size so that a memory array made up of such CMOS memory cells has high density.
OBJECTS AND SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor memory cell employing pass transistors having a low-threshold voltage to improve the performance such as memory access speed.
It is another object of the present invention to provide a semiconductor memory cell which can prevent leakage current in a standby mode of the memory cell and improve the performance of the memory cell by using a “dual-direction” wordline boosting technique.
It is still anther object of the present invention to provide a memory cell employing pass transistors with “high beta” to reduce the size of the memory cell, thus allowing the memory to have a higher density.
To achieve the above and other objects, the present invention provides a semiconductor memory device accessed with wordlines and bitlines, including memory cells of which a memory cell has pass transistors connected to a corresponding wordline and a corresponding pair of bitlines, where the pass transistors are gated by a signal of the corresponding wordline, and a wordline drive unit for selectively driving the wordlines in response to a row address, wherein a wordline driver in the wordline drive unit boosts the corresponding wordline in a positive direction when the corresponding wordline is activated to access the memory cell and boosts the corresponding wordline in a negative direction when the corresponding wordline is inactive.
The semiconductor memory device may also include a row decoder for decoding the row address to provide to the wordline drive unit a signal to select one of the wordlines, a virtual power supply unit connected between the row decoder and a power supply, for providing a virtual supply voltage to the row decoder, and a virtual ground unit connected between the row decoder and a ground, for providing a virtual ground to the row decoder.
In the semiconductor memory device, the pass transistors preferably have a threshold voltage lower than a threshold voltage of transistors other than the pass transistors in the memory cell. And, the wordline driver boosts the corresponding wordline in the negative direction to the extent of substantially preventing a leakage current in the pass transistors.
The wordline driver preferably includes a p-channel MOS (PMOS) transistor disposed in an n-well, an n-channel MOS (NMOS) transistor disposed in a p-well, and an n-band doped with negative ions and disposed under the p-well to isolate the p-well from other p-wells in the wordline driver. The n-well

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