High performance register accesses

Details High performance register accesses High performance register accesses

2007-12-18

2007-12-18

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Plural shift register memory devices

C365S189040

Reexamination Certificate

active

11087838

ABSTRACT:
The use of a bus clock is eliminated in communication between a cpu, or mpu, and a register block. The communication between the cpu/mpu and the register block is made combinatorial, such that the cpu/mpu does not require any acknowledge or wait signal from the register block to know when to proceed with a requested write operation. The register block has both a write request input and a read request input, each of which is separately actuated to initiate a write operation or read operation, respectively. The cpu/mpu initiates a write operation by actuating the write request input while maintaining the read request input negated. The register block responds to actuation of its write request input by getting ready for initiate the requested write operation, and waiting for a signal letting it know if the requested operation is a valid write operation. If the requested write operation is deemed valid, then the register block executes the requested write operation only upon the negation of the write request. Since the write request signal is controlled by the cpu/mpu, the entire write operation is completed within one cpu/mpu operational cycle.

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patent: 2004/0128405 (2004-07-01), Fujita et al.

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