High performance programmable cryptography system

Details High performance programmable cryptography system High performance programmable cryptography system

2005-07-25

2010-11-23

Zand, Kambiz (Department: 2434)

Cryptography

Particular algorithmic function encoding

Reexamination Certificate

active

07840000

ABSTRACT:
The present invention is a method and system for high performance programmable cryptography. In an embodiment of the invention, a cryptography system in accordance with the present invention may include a processor with memory, at least two field programmable gate array (FPGA) blocks and control logic which may be algorithm independent. Programming files storing one or more crypto algorithms may be maintained remotely to the cryptography system whereby the cryptography system may remain not cryptographically controlled when un-programmed. FPGA blocks may be field-programmed to allow execution of a desired crypto algorithm. Additionally, with multiple FPGA logic blocks, programming of a first FPGA block may be simultaneously performed with the execution of a crypto algorithm via a second FPGA block to enable enhanced encryption rate performance.

REFERENCES:
patent: 6101255 (2000-08-01), Harrison et al.
patent: 7200229 (2007-04-01), Spring et al.
patent: 2005/0027970 (2005-02-01), Arnold et al.
patent: 2006/0059286 (2006-03-01), Bertone et al.

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