High performance PNP and NPN transistor structure

Details High performance PNP and NPN transistor structure High performance PNP and NPN transistor structure

1980-05-05

1982-07-13

Edlow, Martin H.

357 49, 357 50, 357 59, 357 35, H01L 2702, H01L 2904

Patent

active

043397670

ABSTRACT:
Disclosed is the fabrication and structure of very small integrated circuit devices of both PNP and NPN types with very high speeds and low power requirements. The structure provides vertical NPN and lateral PNP transistors formed within the same semiconductor chip. The base width of the lateral PNP transistor is very narrow (approximately 300 to 400 nanometers). This narrow dimension is in part obtained by using a well defined chemically vapor deposited (CVD) oxide mask instead of conventional lithographic masking. To eliminate the emitter current injecting into the substrate the P+ emitter and P+ collector of the PNP transistor are bounded by a silicon nitride and silicon dioxide dielectric layer.

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Cheng, IBM Tech. Discl. Bull., vol. 17, No. 1, Jun. 1974, p. 21.
Feth et al., IBM Tech. Discl. Bull., vol. 22, No. 7, Dec. 1979, p. 2939.
Processing For a Lateral PNP In the Submicron Range by A. W. Wieder, IBM Technical Disclosure Bulletin, vol. 21, No. 10, Mar. 1979, pp. 4050-4052.
Self-Aligned Integrated NPN (Vertical) and PNP (Lateral) Structures by T. H. Yeh, IBM Technical Disclosure Bulletin, vol. 22, No. 9, Feb. 1980, pp. 4047-4051.
Method of Producing A Lateral Transistor by H. H. Berger, vol. 23, No. 3, Aug. 1980, pp. 1089-1090.
Improved NPN Process and Structure by F. Barson, IBM Technical Disclosure Bulletin, vol. 23, No. 9, Feb. 1981, pp. 4166-4167.

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